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m68k pull request 20220602
- Fixes and cleanup - Implement TRAP opcodes - Enable halt on 68060 -----BEGIN PGP SIGNATURE----- iQJGBAABCAAwFiEEzS913cjjpNwuT1Fz8ww4vT8vvjwFAmKYpeQSHGxhdXJlbnRA dml2aWVyLmV1AAoJEPMMOL0/L748U+AP/i6EYidZmelIEqOwZTwwzxreF5bTZmAP v0Hxt3Tef3PWJpLnoCXCsd4othCO3PgHcwtrLff+bkWRl0Wt5CYcq+tTu2im7fIN zM7RSO00Pt/va7Ss7Ej8d5P5l7uuFqcBFytnitbsNrvHNK4cQ9PVmOkPnJZe0lYt vA3pUk7giE1KV+/s78Z4VD5CbvwpTRQpDCPDvba7oIP2E9mOELajKtYGh7gvPthx hrG2L5Ou4rYWxJkpZ0mNyYvoPuGRmzgPImdaDMTPLjEYNJMnnqGCRm+ANtzNk+jy d/fE/xJ41xvPAt4Q29yCp0vITuRF468M/elp5hQr/rHc6xtitLCi57FhduY9PuL/ zCMXytgFtnU1C9XhDI/FtQhQxpvEKkZmEJRrAnsuHQKLrHlGoofjBU3whHqfx1zG qw/cdYqx/RUKKxvmoTbk76doaqfVQvBIx2nB6CsHF3pqOpQETK5TYeId49GCkwgR 4DmBPL1RZZpkYxi1KEKprcJWMj1l29UTa2dJ+kt9T2YACRm7MYQurP8OCGoHFIX4 MOr3vdxaqSRU+mE2lWLZWupkZyzFrG/khHSB7A9htTomgbfZLfc0YkHX5kOkHQNq k4ymLpf16F94aau568HVQO8UZV+1FedtRwJL2EWVqkzKri9rSCCeI8I27HVLjwLP YzrHwsMVsjgl =T1g0 -----END PGP SIGNATURE----- Merge tag 'm68k-for-7.1-pull-request' of https://github.com/vivier/qemu-m68k into staging m68k pull request 20220602 - Fixes and cleanup - Implement TRAP opcodes - Enable halt on 68060 # -----BEGIN PGP SIGNATURE----- # # iQJGBAABCAAwFiEEzS913cjjpNwuT1Fz8ww4vT8vvjwFAmKYpeQSHGxhdXJlbnRA # dml2aWVyLmV1AAoJEPMMOL0/L748U+AP/i6EYidZmelIEqOwZTwwzxreF5bTZmAP # v0Hxt3Tef3PWJpLnoCXCsd4othCO3PgHcwtrLff+bkWRl0Wt5CYcq+tTu2im7fIN # zM7RSO00Pt/va7Ss7Ej8d5P5l7uuFqcBFytnitbsNrvHNK4cQ9PVmOkPnJZe0lYt # vA3pUk7giE1KV+/s78Z4VD5CbvwpTRQpDCPDvba7oIP2E9mOELajKtYGh7gvPthx # hrG2L5Ou4rYWxJkpZ0mNyYvoPuGRmzgPImdaDMTPLjEYNJMnnqGCRm+ANtzNk+jy # d/fE/xJ41xvPAt4Q29yCp0vITuRF468M/elp5hQr/rHc6xtitLCi57FhduY9PuL/ # zCMXytgFtnU1C9XhDI/FtQhQxpvEKkZmEJRrAnsuHQKLrHlGoofjBU3whHqfx1zG # qw/cdYqx/RUKKxvmoTbk76doaqfVQvBIx2nB6CsHF3pqOpQETK5TYeId49GCkwgR # 4DmBPL1RZZpkYxi1KEKprcJWMj1l29UTa2dJ+kt9T2YACRm7MYQurP8OCGoHFIX4 # MOr3vdxaqSRU+mE2lWLZWupkZyzFrG/khHSB7A9htTomgbfZLfc0YkHX5kOkHQNq # k4ymLpf16F94aau568HVQO8UZV+1FedtRwJL2EWVqkzKri9rSCCeI8I27HVLjwLP # YzrHwsMVsjgl # =T1g0 # -----END PGP SIGNATURE----- # gpg: Signature made Thu 02 Jun 2022 04:58:28 AM PDT # gpg: using RSA key CD2F75DDC8E3A4DC2E4F5173F30C38BD3F2FBE3C # gpg: issuer "laurent@vivier.eu" # gpg: Good signature from "Laurent Vivier <lvivier@redhat.com>" [undefined] # gpg: aka "Laurent Vivier <laurent@vivier.eu>" [undefined] # gpg: aka "Laurent Vivier (Red Hat) <lvivier@redhat.com>" [undefined] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: CD2F 75DD C8E3 A4DC 2E4F 5173 F30C 38BD 3F2F BE3C * tag 'm68k-for-7.1-pull-request' of https://github.com/vivier/qemu-m68k: target/m68k: Mark helper_raise_exception as noreturn linux-user/strace: Adjust get_thread_area for m68k linux-user/strace: Use is_error in print_syscall_err tests/tcg/m68k: Add trap.c target/m68k: Implement FTRAPcc target/m68k: Implement TRAPV target/m68k: Implement TPF in terms of TRAPcc target/m68k: Implement TRAPcc target/m68k: Fix stack frame for EXCP_ILLEGAL target/m68k: Fix address argument for EXCP_TRACE target/m68k: Fix pc, c flag, and address argument for EXCP_DIV0 target/m68k: Fix address argument for EXCP_CHK target/m68k: Remove retaddr in m68k_interrupt_all linux-user/m68k: Handle EXCP_TRAP1 through EXCP_TRAP15 target/m68k: Fix coding style in m68k_interrupt_all target/m68k: Switch over exception type in m68k_interrupt_all target/m68k: Raise the TRAPn exception with the correct pc target/m68k: Enable halt insn for 68060 target/m68k: Clear mach in m68k_cpu_disas_set_info Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson
commit
1e62a82574
10 changed files with 398 additions and 148 deletions
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@ -3,5 +3,8 @@
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# m68k specific tweaks - specifically masking out broken tests
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#
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VPATH += $(SRC_PATH)/tests/tcg/m68k
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TESTS += trap
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# On m68k Linux supports 4k and 8k pages (but 8k is currently broken)
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EXTRA_RUNS+=run-test-mmap-4096 # run-test-mmap-8192
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129
tests/tcg/m68k/trap.c
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129
tests/tcg/m68k/trap.c
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@ -0,0 +1,129 @@
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/*
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* Test m68k trap addresses.
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*/
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#define _GNU_SOURCE 1
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#include <signal.h>
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#include <assert.h>
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#include <limits.h>
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static int expect_sig;
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static int expect_si_code;
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static void *expect_si_addr;
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static greg_t expect_mc_pc;
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static volatile int got_signal;
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static void sig_handler(int sig, siginfo_t *si, void *puc)
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{
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ucontext_t *uc = puc;
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mcontext_t *mc = &uc->uc_mcontext;
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assert(sig == expect_sig);
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assert(si->si_code == expect_si_code);
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assert(si->si_addr == expect_si_addr);
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assert(mc->gregs[R_PC] == expect_mc_pc);
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got_signal = 1;
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}
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#define FMT_INS [ad] "a"(&expect_si_addr), [pc] "a"(&expect_mc_pc)
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#define FMT0_STR(S) \
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"move.l #1f, (%[ad])\n\tmove.l #1f, (%[pc])\n" S "\n1:\n"
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#define FMT2_STR(S) \
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"move.l #0f, (%[ad])\n\tmove.l #1f, (%[pc])\n" S "\n1:\n"
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#define CHECK_SIG do { assert(got_signal); got_signal = 0; } while (0)
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int main(int argc, char **argv)
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{
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struct sigaction act = {
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.sa_sigaction = sig_handler,
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.sa_flags = SA_SIGINFO
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};
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int t0, t1;
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sigaction(SIGILL, &act, NULL);
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sigaction(SIGTRAP, &act, NULL);
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sigaction(SIGFPE, &act, NULL);
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expect_sig = SIGFPE;
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expect_si_code = FPE_INTOVF;
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asm volatile(FMT2_STR("0:\tchk %0, %1") : : "d"(0), "d"(-1), FMT_INS);
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CHECK_SIG;
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#if 0
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/* FIXME: chk2 not correctly translated. */
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int bounds[2] = { 0, 1 };
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asm volatile(FMT2_STR("0:\tchk2.l %0, %1")
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: : "m"(bounds), "d"(2), FMT_INS);
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CHECK_SIG;
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#endif
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asm volatile(FMT2_STR("cmp.l %0, %1\n0:\ttrapv")
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: : "d"(INT_MIN), "d"(1), FMT_INS);
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CHECK_SIG;
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asm volatile(FMT2_STR("cmp.l %0, %0\n0:\ttrapeq")
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: : "d"(0), FMT_INS);
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CHECK_SIG;
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asm volatile(FMT2_STR("cmp.l %0, %0\n0:\ttrapeq.w #0x1234")
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: : "d"(0), FMT_INS);
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CHECK_SIG;
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asm volatile(FMT2_STR("cmp.l %0, %0\n0:\ttrapeq.l #0x12345678")
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: : "d"(0), FMT_INS);
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CHECK_SIG;
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asm volatile(FMT2_STR("fcmp.x %0, %0\n0:\tftrapeq")
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: : "f"(0.0L), FMT_INS);
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CHECK_SIG;
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expect_si_code = FPE_INTDIV;
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asm volatile(FMT2_STR("0:\tdivs.w %1, %0")
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: "=d"(t0) : "d"(0), "0"(1), FMT_INS);
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CHECK_SIG;
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asm volatile(FMT2_STR("0:\tdivsl.l %2, %1:%0")
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: "=d"(t0), "=d"(t1) : "d"(0), "0"(1), FMT_INS);
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CHECK_SIG;
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expect_sig = SIGILL;
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expect_si_code = ILL_ILLTRP;
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asm volatile(FMT0_STR("trap #1") : : FMT_INS);
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CHECK_SIG;
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asm volatile(FMT0_STR("trap #2") : : FMT_INS);
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CHECK_SIG;
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asm volatile(FMT0_STR("trap #3") : : FMT_INS);
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CHECK_SIG;
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asm volatile(FMT0_STR("trap #4") : : FMT_INS);
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CHECK_SIG;
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asm volatile(FMT0_STR("trap #5") : : FMT_INS);
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CHECK_SIG;
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asm volatile(FMT0_STR("trap #6") : : FMT_INS);
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CHECK_SIG;
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asm volatile(FMT0_STR("trap #7") : : FMT_INS);
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CHECK_SIG;
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asm volatile(FMT0_STR("trap #8") : : FMT_INS);
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CHECK_SIG;
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asm volatile(FMT0_STR("trap #9") : : FMT_INS);
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CHECK_SIG;
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asm volatile(FMT0_STR("trap #10") : : FMT_INS);
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CHECK_SIG;
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asm volatile(FMT0_STR("trap #11") : : FMT_INS);
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CHECK_SIG;
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asm volatile(FMT0_STR("trap #12") : : FMT_INS);
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CHECK_SIG;
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asm volatile(FMT0_STR("trap #13") : : FMT_INS);
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CHECK_SIG;
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asm volatile(FMT0_STR("trap #14") : : FMT_INS);
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CHECK_SIG;
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expect_sig = SIGTRAP;
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expect_si_code = TRAP_BRKPT;
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asm volatile(FMT0_STR("trap #15") : : FMT_INS);
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CHECK_SIG;
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return 0;
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}
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