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pci: pass address space to pci bus when created

Browse source 
This is now done sloppily, via get_system_memory().  Eventually callers
will be converted to stop using that.

Reviewed-by: Anthony Liguori <aliguori@us.ibm.com>
Signed-off-by: Avi Kivity <avi@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
This commit is contained in:
Avi Kivity 2011-07-26 14:26:19 +03:00 • committed by Anthony Liguori
parent 6bd105151a
commit 1e39101c64
22 changed files with 85 additions and 35 deletions
Download patch file Download diff file Expand all files Collapse all files

2
hw/apb_pci.c
View file

@ -34,6 +34,7 @@
#include "rwhandler.h" #include "rwhandler.h"
#include "apb_pci.h" #include "apb_pci.h"
#include "sysemu.h" #include "sysemu.h"
#include "exec-memory.h"
/* debug APB */ /* debug APB */
//#define DEBUG_APB //#define DEBUG_APB
@ -346,6 +347,7 @@ PCIBus *pci_apb_init(target_phys_addr_t special_base,
d->bus = pci_register_bus(&d->busdev.qdev, "pci", d->bus = pci_register_bus(&d->busdev.qdev, "pci",
pci_apb_set_irq, pci_pbm_map_irq, d, pci_apb_set_irq, pci_pbm_map_irq, d,
get_system_memory(),
0, 32); 0, 32);
pci_bus_set_mem_base(d->bus, mem_base); pci_bus_set_mem_base(d->bus, mem_base);

4
hw/bonito.c
View file

@ -42,6 +42,7 @@
#include "mips.h" #include "mips.h"
#include "pci_host.h" #include "pci_host.h"
#include "sysemu.h" #include "sysemu.h"
#include "exec-memory.h"
//#define DEBUG_BONITO //#define DEBUG_BONITO
@ -773,7 +774,8 @@ PCIBus *bonito_init(qemu_irq *pic)
dev = qdev_create(NULL, "Bonito-pcihost"); dev = qdev_create(NULL, "Bonito-pcihost");
pcihost = FROM_SYSBUS(BonitoState, sysbus_from_qdev(dev)); pcihost = FROM_SYSBUS(BonitoState, sysbus_from_qdev(dev));
b = pci_register_bus(&pcihost->busdev.qdev, "pci", pci_bonito_set_irq, b = pci_register_bus(&pcihost->busdev.qdev, "pci", pci_bonito_set_irq,
pci_bonito_map_irq, pic, 0x28, 32); pci_bonito_map_irq, pic, get_system_memory(),
0x28, 32);
pcihost->bus = b; pcihost->bus = b;
qdev_init_nofail(dev); qdev_init_nofail(dev);

5
hw/grackle_pci.c
View file

@ -61,7 +61,8 @@ static void pci_grackle_reset(void *opaque)
{ {
} }
PCIBus *pci_grackle_init(uint32_t base, qemu_irq *pic) PCIBus *pci_grackle_init(uint32_t base, qemu_irq *pic,
MemoryRegion *address_space)
{ {
DeviceState *dev; DeviceState *dev;
SysBusDevice *s; SysBusDevice *s;
@ -74,7 +75,7 @@ PCIBus *pci_grackle_init(uint32_t base, qemu_irq *pic)
d->host_state.bus = pci_register_bus(&d->busdev.qdev, "pci", d->host_state.bus = pci_register_bus(&d->busdev.qdev, "pci",
pci_grackle_set_irq, pci_grackle_set_irq,
pci_grackle_map_irq, pci_grackle_map_irq,
pic, 0, 4); pic, address_space, 0, 4);
pci_create_simple(d->host_state.bus, 0, "grackle"); pci_create_simple(d->host_state.bus, 0, "grackle");

4
hw/gt64xxx.c
View file

@ -27,6 +27,7 @@
#include "pci.h" #include "pci.h"
#include "pci_host.h" #include "pci_host.h"
#include "pc.h" #include "pc.h"
#include "exec-memory.h"
//#define DEBUG //#define DEBUG
@ -1092,7 +1093,8 @@ PCIBus *gt64120_register(qemu_irq *pic)
d = FROM_SYSBUS(GT64120State, s); d = FROM_SYSBUS(GT64120State, s);
d->pci.bus = pci_register_bus(&d->busdev.qdev, "pci", d->pci.bus = pci_register_bus(&d->busdev.qdev, "pci",
gt64120_pci_set_irq, gt64120_pci_map_irq, gt64120_pci_set_irq, gt64120_pci_map_irq,
pic, PCI_DEVFN(18, 0), 4); pic, get_system_memory(),
PCI_DEVFN(18, 0), 4);
d->ISD_handle = cpu_register_io_memory(gt64120_read, gt64120_write, d, d->ISD_handle = cpu_register_io_memory(gt64120_read, gt64120_write, d,
DEVICE_NATIVE_ENDIAN); DEVICE_NATIVE_ENDIAN);

4
hw/pc.h
View file

@ -178,7 +178,9 @@ int pcspk_audio_init(qemu_irq *pic);
struct PCII440FXState; struct PCII440FXState;
typedef struct PCII440FXState PCII440FXState; typedef struct PCII440FXState PCII440FXState;
PCIBus *i440fx_init(PCII440FXState **pi440fx_state, int *piix_devfn, qemu_irq *pic, ram_addr_t ram_size); PCIBus *i440fx_init(PCII440FXState **pi440fx_state, int *piix_devfn,
qemu_irq *pic, MemoryRegion *address_space,
ram_addr_t ram_size);
void i440fx_init_memory_mappings(PCII440FXState *d); void i440fx_init_memory_mappings(PCII440FXState *d);
/* piix4.c */ /* piix4.c */

3
hw/pc_piix.c
View file

@ -128,7 +128,8 @@ static void pc_init1(MemoryRegion *system_memory,
isa_irq = qemu_allocate_irqs(isa_irq_handler, isa_irq_state, 24); isa_irq = qemu_allocate_irqs(isa_irq_handler, isa_irq_state, 24);
if (pci_enabled) { if (pci_enabled) {
pci_bus = i440fx_init(&i440fx_state, &piix3_devfn, isa_irq, ram_size); pci_bus = i440fx_init(&i440fx_state, &piix3_devfn, isa_irq,
system_memory, ram_size);
} else { } else {
pci_bus = NULL; pci_bus = NULL;
i440fx_state = NULL; i440fx_state = NULL;

16
hw/pci.c
View file

@ -263,11 +263,14 @@ int pci_find_domain(const PCIBus *bus)
} }
void pci_bus_new_inplace(PCIBus *bus, DeviceState *parent, void pci_bus_new_inplace(PCIBus *bus, DeviceState *parent,
const char *name, uint8_t devfn_min) const char *name,
MemoryRegion *address_space,
uint8_t devfn_min)
{ {
qbus_create_inplace(&bus->qbus, &pci_bus_info, parent, name); qbus_create_inplace(&bus->qbus, &pci_bus_info, parent, name);
assert(PCI_FUNC(devfn_min) == 0); assert(PCI_FUNC(devfn_min) == 0);
bus->devfn_min = devfn_min; bus->devfn_min = devfn_min;
bus->address_space = address_space;
/* host bridge */ /* host bridge */
QLIST_INIT(&bus->child); QLIST_INIT(&bus->child);
@ -276,13 +279,14 @@ void pci_bus_new_inplace(PCIBus *bus, DeviceState *parent,
vmstate_register(NULL, -1, &vmstate_pcibus, bus); vmstate_register(NULL, -1, &vmstate_pcibus, bus);
} }
PCIBus *pci_bus_new(DeviceState *parent, const char *name, uint8_t devfn_min) PCIBus *pci_bus_new(DeviceState *parent, const char *name,
MemoryRegion *address_space, uint8_t devfn_min)
{ {
PCIBus *bus; PCIBus *bus;
bus = qemu_mallocz(sizeof(*bus)); bus = qemu_mallocz(sizeof(*bus));
bus->qbus.qdev_allocated = 1; bus->qbus.qdev_allocated = 1;
pci_bus_new_inplace(bus, parent, name, devfn_min); pci_bus_new_inplace(bus, parent, name, address_space, devfn_min);
return bus; return bus;
} }
@ -310,11 +314,13 @@ void pci_bus_set_mem_base(PCIBus *bus, target_phys_addr_t base)
PCIBus *pci_register_bus(DeviceState *parent, const char *name, PCIBus *pci_register_bus(DeviceState *parent, const char *name,
pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
void *irq_opaque, uint8_t devfn_min, int nirq) void *irq_opaque,
MemoryRegion *address_space,
uint8_t devfn_min, int nirq)
{ {
PCIBus *bus; PCIBus *bus;
bus = pci_bus_new(parent, name, devfn_min); bus = pci_bus_new(parent, name, address_space, devfn_min);
pci_bus_irqs(bus, set_irq, map_irq, irq_opaque, nirq); pci_bus_irqs(bus, set_irq, map_irq, irq_opaque, nirq);
return bus; return bus;
} }

12
hw/pci.h
View file

@ -5,6 +5,7 @@
#include "qobject.h" #include "qobject.h"
#include "qdev.h" #include "qdev.h"
#include "memory.h"
/* PCI includes legacy ISA access. */ /* PCI includes legacy ISA access. */
#include "isa.h" #include "isa.h"
@ -233,15 +234,20 @@ typedef enum {
typedef int (*pci_hotplug_fn)(DeviceState *qdev, PCIDevice *pci_dev, typedef int (*pci_hotplug_fn)(DeviceState *qdev, PCIDevice *pci_dev,
PCIHotplugState state); PCIHotplugState state);
void pci_bus_new_inplace(PCIBus *bus, DeviceState *parent, void pci_bus_new_inplace(PCIBus *bus, DeviceState *parent,
const char *name, uint8_t devfn_min); const char *name,
PCIBus *pci_bus_new(DeviceState *parent, const char *name, uint8_t devfn_min); MemoryRegion *address_space,
uint8_t devfn_min);
PCIBus *pci_bus_new(DeviceState *parent, const char *name,
MemoryRegion *address_space, uint8_t devfn_min);
void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
void *irq_opaque, int nirq); void *irq_opaque, int nirq);
int pci_bus_get_irq_level(PCIBus *bus, int irq_num); int pci_bus_get_irq_level(PCIBus *bus, int irq_num);
void pci_bus_hotplug(PCIBus *bus, pci_hotplug_fn hotplug, DeviceState *dev); void pci_bus_hotplug(PCIBus *bus, pci_hotplug_fn hotplug, DeviceState *dev);
PCIBus *pci_register_bus(DeviceState *parent, const char *name, PCIBus *pci_register_bus(DeviceState *parent, const char *name,
pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
void *irq_opaque, uint8_t devfn_min, int nirq); void *irq_opaque,
MemoryRegion *address_space,
uint8_t devfn_min, int nirq);
void pci_device_reset(PCIDevice *dev); void pci_device_reset(PCIDevice *dev);
void pci_bus_reset(PCIBus *bus); void pci_bus_reset(PCIBus *bus);

1
hw/pci_host.h
View file

@ -35,6 +35,7 @@ struct PCIHostState {
SysBusDevice busdev; SysBusDevice busdev;
ReadWriteHandler conf_handler; ReadWriteHandler conf_handler;
ReadWriteHandler data_handler; ReadWriteHandler data_handler;
MemoryRegion *address_space;
uint32_t config_reg; uint32_t config_reg;
PCIBus *bus; PCIBus *bus;
}; };

1
hw/pci_internals.h
View file

@ -25,6 +25,7 @@ struct PCIBus {
PCIDevice *devices[PCI_SLOT_MAX * PCI_FUNC_MAX]; PCIDevice *devices[PCI_SLOT_MAX * PCI_FUNC_MAX];
PCIDevice *parent_dev; PCIDevice *parent_dev;
target_phys_addr_t mem_base; target_phys_addr_t mem_base;
MemoryRegion *address_space;
QLIST_HEAD(, PCIBus) child; /* this will be replaced by qdev later */ QLIST_HEAD(, PCIBus) child; /* this will be replaced by qdev later */
QLIST_ENTRY(PCIBus) sibling;/* this will be replaced by qdev later */ QLIST_ENTRY(PCIBus) sibling;/* this will be replaced by qdev later */

13
hw/piix_pci.c
View file

@ -241,7 +241,9 @@ static int i440fx_initfn(PCIDevice *dev)
static PCIBus *i440fx_common_init(const char *device_name, static PCIBus *i440fx_common_init(const char *device_name,
PCII440FXState **pi440fx_state, PCII440FXState **pi440fx_state,
int *piix3_devfn, int *piix3_devfn,
qemu_irq *pic, ram_addr_t ram_size) qemu_irq *pic,
MemoryRegion *address_space,
ram_addr_t ram_size)
{ {
DeviceState *dev; DeviceState *dev;
PCIBus *b; PCIBus *b;
@ -251,7 +253,8 @@ static PCIBus *i440fx_common_init(const char *device_name,
dev = qdev_create(NULL, "i440FX-pcihost"); dev = qdev_create(NULL, "i440FX-pcihost");
s = FROM_SYSBUS(I440FXState, sysbus_from_qdev(dev)); s = FROM_SYSBUS(I440FXState, sysbus_from_qdev(dev));
b = pci_bus_new(&s->busdev.qdev, NULL, 0); s->address_space = address_space;
b = pci_bus_new(&s->busdev.qdev, NULL, s->address_space, 0);
s->bus = b; s->bus = b;
qdev_init_nofail(dev); qdev_init_nofail(dev);
@ -288,11 +291,13 @@ static PCIBus *i440fx_common_init(const char *device_name,
} }
PCIBus *i440fx_init(PCII440FXState **pi440fx_state, int *piix3_devfn, PCIBus *i440fx_init(PCII440FXState **pi440fx_state, int *piix3_devfn,
qemu_irq *pic, ram_addr_t ram_size) qemu_irq *pic, MemoryRegion *address_space,
ram_addr_t ram_size)
{ {
PCIBus *b; PCIBus *b;
b = i440fx_common_init("i440FX", pi440fx_state, piix3_devfn, pic, ram_size); b = i440fx_common_init("i440FX", pi440fx_state, piix3_devfn, pic,
address_space, ram_size);
return b; return b;
} }

5
hw/ppc4xx_pci.c
View file

@ -24,6 +24,7 @@
#include "ppc4xx.h" #include "ppc4xx.h"
#include "pci.h" #include "pci.h"
#include "pci_host.h" #include "pci_host.h"
#include "exec-memory.h"
#undef DEBUG #undef DEBUG
#ifdef DEBUG #ifdef DEBUG
@ -345,7 +346,9 @@ PCIBus *ppc4xx_pci_init(CPUState *env, qemu_irq pci_irqs[4],
controller->pci_state.bus = pci_register_bus(NULL, "pci", controller->pci_state.bus = pci_register_bus(NULL, "pci",
ppc4xx_pci_set_irq, ppc4xx_pci_set_irq,
ppc4xx_pci_map_irq, ppc4xx_pci_map_irq,
pci_irqs, 0, 4); pci_irqs,
get_system_memory(),
0, 4);
controller->pci_dev = pci_register_device(controller->pci_state.bus, controller->pci_dev = pci_register_device(controller->pci_state.bus,
"host bridge", sizeof(PCIDevice), "host bridge", sizeof(PCIDevice),

9
hw/ppc_mac.h
View file

@ -25,6 +25,8 @@
#if !defined(__PPC_MAC_H__) #if !defined(__PPC_MAC_H__)
#define __PPC_MAC_H__ #define __PPC_MAC_H__
#include "memory.h"
/* SMP is not enabled, for now */ /* SMP is not enabled, for now */
#define MAX_CPUS 1 #define MAX_CPUS 1
@ -52,11 +54,12 @@ qemu_irq *heathrow_pic_init(int *pmem_index,
int nb_cpus, qemu_irq **irqs); int nb_cpus, qemu_irq **irqs);
/* Grackle PCI */ /* Grackle PCI */
PCIBus *pci_grackle_init(uint32_t base, qemu_irq *pic); PCIBus *pci_grackle_init(uint32_t base, qemu_irq *pic,
MemoryRegion *address_space);
/* UniNorth PCI */ /* UniNorth PCI */
PCIBus *pci_pmac_init(qemu_irq *pic); PCIBus *pci_pmac_init(qemu_irq *pic, MemoryRegion *address_space);
PCIBus *pci_pmac_u3_init(qemu_irq *pic); PCIBus *pci_pmac_u3_init(qemu_irq *pic, MemoryRegion *address_space);
/* Mac NVRAM */ /* Mac NVRAM */
typedef struct MacIONVRAMState MacIONVRAMState; typedef struct MacIONVRAMState MacIONVRAMState;

5
hw/ppc_newworld.c
View file

@ -67,6 +67,7 @@
#include "kvm_ppc.h" #include "kvm_ppc.h"
#include "hw/usb.h" #include "hw/usb.h"
#include "blockdev.h" #include "blockdev.h"
#include "exec-memory.h"
#define MAX_IDE_BUS 2 #define MAX_IDE_BUS 2
#define CFG_ADDR 0xf0000510 #define CFG_ADDR 0xf0000510
@ -317,10 +318,10 @@ static void ppc_core99_init (ram_addr_t ram_size,
pic = openpic_init(NULL, &pic_mem_index, smp_cpus, openpic_irqs, NULL); pic = openpic_init(NULL, &pic_mem_index, smp_cpus, openpic_irqs, NULL);
if (PPC_INPUT(env) == PPC_FLAGS_INPUT_970) { if (PPC_INPUT(env) == PPC_FLAGS_INPUT_970) {
/* 970 gets a U3 bus */ /* 970 gets a U3 bus */
pci_bus = pci_pmac_u3_init(pic); pci_bus = pci_pmac_u3_init(pic, get_system_memory());
machine_arch = ARCH_MAC99_U3; machine_arch = ARCH_MAC99_U3;
} else { } else {
pci_bus = pci_pmac_init(pic); pci_bus = pci_pmac_init(pic, get_system_memory());
machine_arch = ARCH_MAC99; machine_arch = ARCH_MAC99;
} }
/* init basic PC hardware */ /* init basic PC hardware */

3
hw/ppc_oldworld.c
View file

@ -43,6 +43,7 @@
#include "kvm.h" #include "kvm.h"
#include "kvm_ppc.h" #include "kvm_ppc.h"
#include "blockdev.h" #include "blockdev.h"
#include "exec-memory.h"
#define MAX_IDE_BUS 2 #define MAX_IDE_BUS 2
#define CFG_ADDR 0xf0000510 #define CFG_ADDR 0xf0000510
@ -233,7 +234,7 @@ static void ppc_heathrow_init (ram_addr_t ram_size,
hw_error("Only 6xx bus is supported on heathrow machine\n"); hw_error("Only 6xx bus is supported on heathrow machine\n");
} }
pic = heathrow_pic_init(&pic_mem_index, 1, heathrow_irqs); pic = heathrow_pic_init(&pic_mem_index, 1, heathrow_irqs);
pci_bus = pci_grackle_init(0xfec00000, pic); pci_bus = pci_grackle_init(0xfec00000, pic, get_system_memory());
pci_vga_init(pci_bus); pci_vga_init(pci_bus);
escc_mem_index = escc_init(0x80013000, pic[0x0f], pic[0x10], serial_hds[0], escc_mem_index = escc_init(0x80013000, pic[0x0f], pic[0x10], serial_hds[0],

3
hw/ppc_prep.c
View file

@ -38,6 +38,7 @@
#include "loader.h" #include "loader.h"
#include "mc146818rtc.h" #include "mc146818rtc.h"
#include "blockdev.h" #include "blockdev.h"
#include "exec-memory.h"
//#define HARD_DEBUG_PPC_IO //#define HARD_DEBUG_PPC_IO
//#define DEBUG_PPC_IO //#define DEBUG_PPC_IO
@ -648,7 +649,7 @@ static void ppc_prep_init (ram_addr_t ram_size,
hw_error("Only 6xx bus is supported on PREP machine\n"); hw_error("Only 6xx bus is supported on PREP machine\n");
} }
i8259 = i8259_init(first_cpu->irq_inputs[PPC6xx_INPUT_INT]); i8259 = i8259_init(first_cpu->irq_inputs[PPC6xx_INPUT_INT]);
pci_bus = pci_prep_init(i8259); pci_bus = pci_prep_init(i8259, get_system_memory());
/* Hmm, prep has no pci-isa bridge ??? */ /* Hmm, prep has no pci-isa bridge ??? */
isa_bus_new(NULL); isa_bus_new(NULL);
isa_bus_irqs(i8259); isa_bus_irqs(i8259);

6
hw/ppce500_pci.c
View file

@ -274,12 +274,15 @@ static void e500_pci_map(SysBusDevice *dev, target_phys_addr_t base)
s->reg); s->reg);
} }
#include "exec-memory.h"
static int e500_pcihost_initfn(SysBusDevice *dev) static int e500_pcihost_initfn(SysBusDevice *dev)
{ {
PCIHostState *h; PCIHostState *h;
PPCE500PCIState *s; PPCE500PCIState *s;
PCIBus *b; PCIBus *b;
int i; int i;
MemoryRegion *address_space = get_system_memory();
h = FROM_SYSBUS(PCIHostState, sysbus_from_qdev(dev)); h = FROM_SYSBUS(PCIHostState, sysbus_from_qdev(dev));
s = DO_UPCAST(PPCE500PCIState, pci_state, h); s = DO_UPCAST(PPCE500PCIState, pci_state, h);
@ -289,7 +292,8 @@ static int e500_pcihost_initfn(SysBusDevice *dev)
} }
b = pci_register_bus(&s->pci_state.busdev.qdev, NULL, mpc85xx_pci_set_irq, b = pci_register_bus(&s->pci_state.busdev.qdev, NULL, mpc85xx_pci_set_irq,
mpc85xx_pci_map_irq, s->irq, PCI_DEVFN(0x11, 0), 4); mpc85xx_pci_map_irq, s->irq, address_space,
PCI_DEVFN(0x11, 0), 4);
s->pci_state.bus = b; s->pci_state.bus = b;
pci_create_simple(b, 0, "e500-host-bridge"); pci_create_simple(b, 0, "e500-host-bridge");

5
hw/prep_pci.c
View file

@ -110,7 +110,7 @@ static void prep_set_irq(void *opaque, int irq_num, int level)
qemu_set_irq(pic[(irq_num & 1) ? 11 : 9] , level); qemu_set_irq(pic[(irq_num & 1) ? 11 : 9] , level);
} }
PCIBus *pci_prep_init(qemu_irq *pic) PCIBus *pci_prep_init(qemu_irq *pic, MemoryRegion *address_space)
{ {
PREPPCIState *s; PREPPCIState *s;
PCIDevice *d; PCIDevice *d;
@ -118,7 +118,8 @@ PCIBus *pci_prep_init(qemu_irq *pic)
s = qemu_mallocz(sizeof(PREPPCIState)); s = qemu_mallocz(sizeof(PREPPCIState));
s->bus = pci_register_bus(NULL, "pci", s->bus = pci_register_bus(NULL, "pci",
prep_set_irq, prep_map_irq, pic, 0, 4); prep_set_irq, prep_map_irq, pic,
address_space, 0, 4);
pci_host_conf_register_ioport(0xcf8, s); pci_host_conf_register_ioport(0xcf8, s);

3
hw/prep_pci.h
View file

@ -2,7 +2,8 @@
#define QEMU_PREP_PCI_H #define QEMU_PREP_PCI_H
#include "qemu-common.h" #include "qemu-common.h"
#include "memory.h"
PCIBus *pci_prep_init(qemu_irq *pic); PCIBus *pci_prep_init(qemu_irq *pic, MemoryRegion *address_space);
#endif #endif

4
hw/sh_pci.c
View file

@ -26,6 +26,7 @@
#include "pci.h" #include "pci.h"
#include "pci_host.h" #include "pci_host.h"
#include "bswap.h" #include "bswap.h"
#include "exec-memory.h"
typedef struct SHPCIState { typedef struct SHPCIState {
SysBusDevice busdev; SysBusDevice busdev;
@ -127,7 +128,8 @@ static int sh_pci_init_device(SysBusDevice *dev)
} }
s->bus = pci_register_bus(&s->busdev.qdev, "pci", s->bus = pci_register_bus(&s->busdev.qdev, "pci",
sh_pci_set_irq, sh_pci_map_irq, sh_pci_set_irq, sh_pci_map_irq,
s->irq, PCI_DEVFN(0, 0), 4); s->irq, get_system_memory(),
PCI_DEVFN(0, 0), 4);
s->memconfig = cpu_register_io_memory(sh_pci_reg.r, sh_pci_reg.w, s->memconfig = cpu_register_io_memory(sh_pci_reg.r, sh_pci_reg.w,
s, DEVICE_NATIVE_ENDIAN); s, DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio_cb(dev, 0x224, sh_pci_map); sysbus_init_mmio_cb(dev, 0x224, sh_pci_map);

10
hw/unin_pci.c
View file

@ -201,7 +201,7 @@ static int pci_unin_internal_init_device(SysBusDevice *dev)
return 0; return 0;
} }
PCIBus *pci_pmac_init(qemu_irq *pic) PCIBus *pci_pmac_init(qemu_irq *pic, MemoryRegion *address_space)
{ {
DeviceState *dev; DeviceState *dev;
SysBusDevice *s; SysBusDevice *s;
@ -215,7 +215,8 @@ PCIBus *pci_pmac_init(qemu_irq *pic)
d = FROM_SYSBUS(UNINState, s); d = FROM_SYSBUS(UNINState, s);
d->host_state.bus = pci_register_bus(&d->busdev.qdev, "pci", d->host_state.bus = pci_register_bus(&d->busdev.qdev, "pci",
pci_unin_set_irq, pci_unin_map_irq, pci_unin_set_irq, pci_unin_map_irq,
pic, PCI_DEVFN(11, 0), 4); pic, address_space,
PCI_DEVFN(11, 0), 4);
#if 0 #if 0
pci_create_simple(d->host_state.bus, PCI_DEVFN(11, 0), "uni-north"); pci_create_simple(d->host_state.bus, PCI_DEVFN(11, 0), "uni-north");
@ -252,7 +253,7 @@ PCIBus *pci_pmac_init(qemu_irq *pic)
return d->host_state.bus; return d->host_state.bus;
} }
PCIBus *pci_pmac_u3_init(qemu_irq *pic) PCIBus *pci_pmac_u3_init(qemu_irq *pic, MemoryRegion *address_space)
{ {
DeviceState *dev; DeviceState *dev;
SysBusDevice *s; SysBusDevice *s;
@ -267,7 +268,8 @@ PCIBus *pci_pmac_u3_init(qemu_irq *pic)
d->host_state.bus = pci_register_bus(&d->busdev.qdev, "pci", d->host_state.bus = pci_register_bus(&d->busdev.qdev, "pci",
pci_unin_set_irq, pci_unin_map_irq, pci_unin_set_irq, pci_unin_map_irq,
pic, PCI_DEVFN(11, 0), 4); pic, address_space,
PCI_DEVFN(11, 0), 4);
sysbus_mmio_map(s, 0, 0xf0800000); sysbus_mmio_map(s, 0, 0xf0800000);
sysbus_mmio_map(s, 1, 0xf0c00000); sysbus_mmio_map(s, 1, 0xf0c00000);

2
hw/versatile_pci.c
View file

@ -10,6 +10,7 @@
#include "sysbus.h" #include "sysbus.h"
#include "pci.h" #include "pci.h"
#include "pci_host.h" #include "pci_host.h"
#include "exec-memory.h"
typedef struct { typedef struct {
SysBusDevice busdev; SysBusDevice busdev;
@ -111,6 +112,7 @@ static int pci_vpb_init(SysBusDevice *dev)
} }
bus = pci_register_bus(&dev->qdev, "pci", bus = pci_register_bus(&dev->qdev, "pci",
pci_vpb_set_irq, pci_vpb_map_irq, s->irq, pci_vpb_set_irq, pci_vpb_map_irq, s->irq,
get_system_memory(),
PCI_DEVFN(11, 0), 4); PCI_DEVFN(11, 0), 4);
/* ??? Register memory space. */ /* ??? Register memory space. */