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target/riscv: Change gen_goto_tb to work on displacements

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Reduce reliance on absolute value to prepare for PC-relative translation.

Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230526072124.298466-4-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Weiwei Li 2023-05-26 15:21:20 +08:00 • committed by Alistair Francis
parent 8ef23a329a
commit 1df8497b9d
2 changed files with 7 additions and 5 deletions
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4
target/riscv/insn_trans/trans_rvi.c.inc
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@ -171,7 +171,7 @@ static bool gen_branch(DisasContext *ctx, arg_b *a, TCGCond cond)
} else {
tcg_gen_brcond_tl(cond, src1, src2, l);
}
gen_goto_tb(ctx, 1, ctx->pc_succ_insn);
gen_goto_tb(ctx, 1, ctx->cur_insn_len);
gen_set_label(l); /* branch taken */
@ -183,7 +183,7 @@ static bool gen_branch(DisasContext *ctx, arg_b *a, TCGCond cond)
gen_pc_plus_diff(target_pc, ctx, next_pc);
gen_exception_inst_addr_mis(ctx, target_pc);
} else {
gen_goto_tb(ctx, 0, ctx->base.pc_next + a->imm);
gen_goto_tb(ctx, 0, a->imm);
}
ctx->base.is_jmp = DISAS_NORETURN;