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util: Enhance flush_icache_range with separate data pointer

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We are shortly going to have a split rw/rx jit buffer.  Depending
on the host, we need to flush the dcache at the rw data pointer and
flush the icache at the rx code pointer.

For now, the two passed pointers are identical, so there is no
effective change in behaviour.

Reviewed-by: Joelle van Dyne <j@getutm.app>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2020-12-12 10:38:21 -06:00
parent df5d2b1658
commit 1da8de39a3
9 changed files with 51 additions and 30 deletions
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15
include/qemu/cacheflush.h
View file

@ -8,16 +8,27 @@
#ifndef QEMU_CACHEFLUSH_H
#define QEMU_CACHEFLUSH_H
/**
* flush_idcache_range:
* @rx: instruction address
* @rw: data address
* @len: length to flush
*
* Flush @len bytes of the data cache at @rw and the icache at @rx
* to bring them in sync. The two addresses may be different virtual
* mappings of the same physical page(s).
*/
#if defined(__i386__) || defined(__x86_64__) || defined(__s390__)
static inline void flush_icache_range(uintptr_t start, uintptr_t stop)
static inline void flush_idcache_range(uintptr_t rx, uintptr_t rw, size_t len)
{
/* icache is coherent and does not require flushing. */
}
#else
void flush_icache_range(uintptr_t start, uintptr_t stop);
void flush_idcache_range(uintptr_t rx, uintptr_t rw, size_t len);
#endif