motorhead/qemu
1
0
Fork 0
mirror of https://github.com/Motorhead1991/qemu.git synced 2025-12-11 16:00:50 -07:00
Code Issues Projects Releases Packages Wiki Activity Actions

target/riscv: th: make CSR insertion test a bit more intuitive

Browse source 
In preparation for generalizing the custom CSR functionality,
make the test return bool instead of int.  Make the insertion_test
optional, too.

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
This commit is contained in:
Paolo Bonzini 2025-02-06 17:39:49 +01:00
parent 5a62948c91
commit 1d84c2401c
1 changed files with 4 additions and 9 deletions
Download patch file Download diff file Expand all files Collapse all files

13
target/riscv/th_csr.c
View file

@ -29,7 +29,7 @@
typedef struct {
int csrno;
int (*insertion_test)(RISCVCPU *cpu);
bool (*insertion_test)(RISCVCPU *cpu);
riscv_csr_operations csr_ops;
} riscv_csr;
@ -42,13 +42,9 @@ static RISCVException smode(CPURISCVState *env, int csrno)
return RISCV_EXCP_ILLEGAL_INST;
}
static int test_thead_mvendorid(RISCVCPU *cpu)
static bool test_thead_mvendorid(RISCVCPU *cpu)
{
if (cpu->cfg.mvendorid != THEAD_VENDOR_ID) {
return -1;
}
return 0;
return cpu->cfg.mvendorid == THEAD_VENDOR_ID;
}
static RISCVException read_th_sxstatus(CPURISCVState *env, int csrno,
@ -66,13 +62,12 @@ static riscv_csr th_csr_list[] = {
.csr_ops = { "th.sxstatus", smode, read_th_sxstatus }
}
};
void th_register_custom_csrs(RISCVCPU *cpu)
{
for (size_t i = 0; i < ARRAY_SIZE(th_csr_list); i++) {
int csrno = th_csr_list[i].csrno;
riscv_csr_operations *csr_ops = &th_csr_list[i].csr_ops;
if (!th_csr_list[i].insertion_test(cpu)) {
if (!th_csr_list[i].insertion_test || th_csr_list[i].insertion_test(cpu)) {
riscv_set_csr_ops(csrno, csr_ops);
}
}