docs/specs: add riscv-iommu-sys information

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20241106133407.604587-8-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Daniel Henrique Barboza 2024-11-06 10:34:07 -03:00 committed by Alistair Francis
parent 9afd26715e
commit 1c187ad5c0
2 changed files with 37 additions and 3 deletions

View file

@ -6,9 +6,9 @@ RISC-V IOMMU support for RISC-V machines
QEMU implements a RISC-V IOMMU emulation based on the RISC-V IOMMU spec
version 1.0 `iommu1.0`_.
The emulation includes a PCI reference device, riscv-iommu-pci, that QEMU
RISC-V boards can use. The 'virt' RISC-V machine is compatible with this
device.
The emulation includes a PCI reference device (riscv-iommu-pci) and a platform
bus device (riscv-iommu-sys) that QEMU RISC-V boards can use. The 'virt'
RISC-V machine is compatible with both devices.
riscv-iommu-pci reference device
--------------------------------
@ -83,6 +83,30 @@ Several options are available to control the capabilities of the device, namely:
- "s-stage": enable s-stage support
- "g-stage": enable g-stage support
riscv-iommu-sys device
----------------------
This device implements the RISC-V IOMMU emulation as a platform bus device that
RISC-V boards can use.
For the 'virt' board the device is disabled by default. To enable it use the
'iommu-sys' machine option:
.. code-block:: bash
$ qemu-system-riscv64 -M virt,iommu-sys=on (...)
There is no options to configure the capabilities of this device in the 'virt'
board using the QEMU command line. The device is configured with the following
riscv-iommu options:
- "ioatc-limit": default value (2Mb)
- "intremap": enabled
- "ats": enabled
- "off": on (DMA disabled)
- "s-stage": enabled
- "g-stage": enabled
.. _iommu1.0: https://github.com/riscv-non-isa/riscv-iommu/releases/download/v1.0/riscv-iommu.pdf
.. _linux-v8: https://lore.kernel.org/linux-riscv/cover.1718388908.git.tjeznach@rivosinc.com/