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virtio,pc,pci: features, cleanups
infrastructure for vhost-vdpa shadow work piix south bridge rework reconnect for vhost-user-scsi dummy ACPI QTG DSM for cxl tests, cleanups, fixes all over the place Signed-off-by: Michael S. Tsirkin <mst@redhat.com> -----BEGIN PGP SIGNATURE----- iQFDBAABCAAtFiEEXQn9CHHI+FuUyooNKB8NuNKNVGkFAmU06PMPHG1zdEByZWRo YXQuY29tAAoJECgfDbjSjVRpNIsH/0DlKti86VZLJ6PbNqsnKxoK2gg05TbEhPZU pQ+RPDaCHpFBsLC5qsoMJwvaEQFe0e49ZFemw7bXRzBxgmbbNnZ9ArCIPqT+rvQd 7UBmyC+kacVyybZatq69aK2BHKFtiIRlT78d9Izgtjmp8V7oyKoz14Esh8wkE+FT ypHUa70Addi6alNm6BVkm7bxZxi0Wrmf3THqF8ViYvufzHKl7JR5e17fKWEG0BqV 9W7AeHMnzJ7jkTvBGUw7g5EbzFn7hPLTbO4G/VW97k0puS4WRX5aIMkVhUazsRIa zDOuXCCskUWuRapiCwY0E4g7cCaT8/JR6JjjBaTgkjJgvo5Y8Eg= =ILek -----END PGP SIGNATURE----- Merge tag 'for_upstream' of https://git.kernel.org/pub/scm/virt/kvm/mst/qemu into staging virtio,pc,pci: features, cleanups infrastructure for vhost-vdpa shadow work piix south bridge rework reconnect for vhost-user-scsi dummy ACPI QTG DSM for cxl tests, cleanups, fixes all over the place Signed-off-by: Michael S. Tsirkin <mst@redhat.com> # -----BEGIN PGP SIGNATURE----- # # iQFDBAABCAAtFiEEXQn9CHHI+FuUyooNKB8NuNKNVGkFAmU06PMPHG1zdEByZWRo # YXQuY29tAAoJECgfDbjSjVRpNIsH/0DlKti86VZLJ6PbNqsnKxoK2gg05TbEhPZU # pQ+RPDaCHpFBsLC5qsoMJwvaEQFe0e49ZFemw7bXRzBxgmbbNnZ9ArCIPqT+rvQd # 7UBmyC+kacVyybZatq69aK2BHKFtiIRlT78d9Izgtjmp8V7oyKoz14Esh8wkE+FT # ypHUa70Addi6alNm6BVkm7bxZxi0Wrmf3THqF8ViYvufzHKl7JR5e17fKWEG0BqV # 9W7AeHMnzJ7jkTvBGUw7g5EbzFn7hPLTbO4G/VW97k0puS4WRX5aIMkVhUazsRIa # zDOuXCCskUWuRapiCwY0E4g7cCaT8/JR6JjjBaTgkjJgvo5Y8Eg= # =ILek # -----END PGP SIGNATURE----- # gpg: Signature made Sun 22 Oct 2023 02:18:43 PDT # gpg: using RSA key 5D09FD0871C8F85B94CA8A0D281F0DB8D28D5469 # gpg: issuer "mst@redhat.com" # gpg: Good signature from "Michael S. Tsirkin <mst@kernel.org>" [full] # gpg: aka "Michael S. Tsirkin <mst@redhat.com>" [full] # Primary key fingerprint: 0270 606B 6F3C DF3D 0B17 0970 C350 3912 AFBE 8E67 # Subkey fingerprint: 5D09 FD08 71C8 F85B 94CA 8A0D 281F 0DB8 D28D 5469 * tag 'for_upstream' of https://git.kernel.org/pub/scm/virt/kvm/mst/qemu: (62 commits) intel-iommu: Report interrupt remapping faults, fix return value MAINTAINERS: Add include/hw/intc/i8259.h to the PC chip section vhost-user: Fix protocol feature bit conflict tests/acpi: Update DSDT.cxl with QTG DSM hw/cxl: Add QTG _DSM support for ACPI0017 device tests/acpi: Allow update of DSDT.cxl hw/i386/cxl: ensure maxram is greater than ram size for calculating cxl range vhost-user: fix lost reconnect vhost-user-scsi: start vhost when guest kicks vhost-user-scsi: support reconnect to backend vhost: move and rename the conn retry times vhost-user-common: send get_inflight_fd once hw/i386/pc_piix: Make PIIX4 south bridge usable in PC machine hw/isa/piix: Implement multi-process QEMU support also for PIIX4 hw/isa/piix: Resolve duplicate code regarding PCI interrupt wiring hw/isa/piix: Reuse PIIX3's PCI interrupt triggering in PIIX4 hw/isa/piix: Rename functions to be shared for PCI interrupt triggering hw/isa/piix: Reuse PIIX3 base class' realize method in PIIX4 hw/isa/piix: Share PIIX3's base class with PIIX4 hw/isa/piix: Harmonize names of reset control memory regions ... Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
This commit is contained in:
Stefan Hajnoczi
commit
1b4a5a20da
43 changed files with 1218 additions and 836 deletions
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@ -2793,6 +2793,8 @@ int64_t address_space_cache_init(MemoryRegionCache *cache,
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static inline void address_space_cache_init_empty(MemoryRegionCache *cache)
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{
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cache->mrs.mr = NULL;
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/* There is no real need to initialize fv, but it makes Coverity happy. */
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cache->fv = NULL;
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}
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/**
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@ -25,5 +25,6 @@ void cxl_build_cedt(GArray *table_offsets, GArray *table_data,
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BIOSLinker *linker, const char *oem_id,
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const char *oem_table_id, CXLState *cxl_state);
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void build_cxl_osc_method(Aml *dev);
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void build_cxl_dsm_method(Aml *dev);
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#endif
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@ -42,6 +42,7 @@ typedef struct PCMachineState {
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uint64_t max_ram_below_4g;
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OnOffAuto vmport;
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SmbiosEntryPointType smbios_entry_point_type;
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const char *south_bridge;
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bool acpi_build_enabled;
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bool smbus_enabled;
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@ -92,6 +93,7 @@ struct PCMachineClass {
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/* Device configuration: */
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bool pci_enabled;
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bool kvmclock_enabled;
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const char *default_south_bridge;
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/* Compat options: */
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@ -13,7 +13,10 @@
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#define HW_SOUTHBRIDGE_PIIX_H
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#include "hw/pci/pci_device.h"
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#include "hw/acpi/piix4.h"
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#include "hw/ide/pci.h"
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#include "hw/rtc/mc146818rtc.h"
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#include "hw/usb/hcd-uhci.h"
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/* PIRQRC[A:D]: PIRQx Route Control Registers */
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#define PIIX_PIRQCA 0x60
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@ -27,7 +30,6 @@
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*/
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#define PIIX_RCR_IOPORT 0xcf9
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#define PIIX_NUM_PIC_IRQS 16 /* i8259 * 2 */
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#define PIIX_NUM_PIRQS 4ULL /* PIRQ[A-D] */
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struct PIIXState {
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@ -39,32 +41,42 @@ struct PIIXState {
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* So one PIC level is tracked by PIIX_NUM_PIRQS bits.
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*
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* PIRQ is mapped to PIC pins, we track it by
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* PIIX_NUM_PIRQS * PIIX_NUM_PIC_IRQS = 64 bits with
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* PIIX_NUM_PIRQS * ISA_NUM_IRQS = 64 bits with
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* pic_irq * PIIX_NUM_PIRQS + pirq
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*/
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#if PIIX_NUM_PIC_IRQS * PIIX_NUM_PIRQS > 64
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#if ISA_NUM_IRQS * PIIX_NUM_PIRQS > 64
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#error "unable to encode pic state in 64bit in pic_levels."
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#endif
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uint64_t pic_levels;
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qemu_irq *pic;
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qemu_irq cpu_intr;
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qemu_irq isa_irqs_in[ISA_NUM_IRQS];
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/* This member isn't used. Just for save/load compatibility */
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int32_t pci_irq_levels_vmstate[PIIX_NUM_PIRQS];
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MC146818RtcState rtc;
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PCIIDEState ide;
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UHCIState uhci;
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PIIX4PMState pm;
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uint32_t smb_io_base;
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/* Reset Control Register contents */
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uint8_t rcr;
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/* IO memory region for Reset Control Register (PIIX_RCR_IOPORT) */
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MemoryRegion rcr_mem;
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};
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typedef struct PIIXState PIIX3State;
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#define TYPE_PIIX3_PCI_DEVICE "pci-piix3"
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DECLARE_INSTANCE_CHECKER(PIIX3State, PIIX3_PCI_DEVICE,
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TYPE_PIIX3_PCI_DEVICE)
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bool has_acpi;
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bool has_pic;
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bool has_pit;
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bool has_usb;
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bool smm_enabled;
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};
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#define TYPE_PIIX_PCI_DEVICE "pci-piix"
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OBJECT_DECLARE_SIMPLE_TYPE(PIIXState, PIIX_PCI_DEVICE)
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#define TYPE_PIIX3_DEVICE "PIIX3"
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#define TYPE_PIIX4_PCI_DEVICE "piix4-isa"
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@ -39,7 +39,7 @@ struct VHostSCSICommon {
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struct vhost_inflight *inflight;
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};
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int vhost_scsi_common_start(VHostSCSICommon *vsc);
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int vhost_scsi_common_start(VHostSCSICommon *vsc, Error **errp);
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void vhost_scsi_common_stop(VHostSCSICommon *vsc);
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char *vhost_scsi_common_get_fw_dev_path(FWPathProvider *p, BusState *bus,
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DeviceState *dev);
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@ -28,7 +28,13 @@ OBJECT_DECLARE_SIMPLE_TYPE(VHostUserSCSI, VHOST_USER_SCSI)
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struct VHostUserSCSI {
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VHostSCSICommon parent_obj;
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/* Properties */
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bool connected;
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bool started_vu;
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VhostUserState vhost_user;
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struct vhost_virtqueue *vhost_vqs;
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};
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#endif /* VHOST_USER_SCSI_H */
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@ -29,7 +29,8 @@ enum VhostUserProtocolFeature {
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VHOST_USER_PROTOCOL_F_INBAND_NOTIFICATIONS = 14,
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VHOST_USER_PROTOCOL_F_CONFIGURE_MEM_SLOTS = 15,
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VHOST_USER_PROTOCOL_F_STATUS = 16,
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VHOST_USER_PROTOCOL_F_SHARED_OBJECT = 17,
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/* Feature 17 reserved for VHOST_USER_PROTOCOL_F_XEN_MMAP. */
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VHOST_USER_PROTOCOL_F_SHARED_OBJECT = 18,
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VHOST_USER_PROTOCOL_F_MAX
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};
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@ -106,6 +107,7 @@ typedef void (*vu_async_close_fn)(DeviceState *cb);
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void vhost_user_async_close(DeviceState *d,
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CharBackend *chardev, struct vhost_dev *vhost,
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vu_async_close_fn cb);
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vu_async_close_fn cb,
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IOEventHandler *event_cb);
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#endif
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@ -8,6 +8,8 @@
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#define VHOST_F_DEVICE_IOTLB 63
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#define VHOST_USER_F_PROTOCOL_FEATURES 30
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#define VU_REALIZE_CONN_RETRIES 3
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/* Generic structures common for any vhost based device. */
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struct vhost_inflight {
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@ -339,4 +341,14 @@ int vhost_dev_set_inflight(struct vhost_dev *dev,
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int vhost_dev_get_inflight(struct vhost_dev *dev, uint16_t queue_size,
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struct vhost_inflight *inflight);
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bool vhost_dev_has_iommu(struct vhost_dev *dev);
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#ifdef CONFIG_VHOST
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int vhost_reset_device(struct vhost_dev *hdev);
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#else
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static inline int vhost_reset_device(struct vhost_dev *hdev)
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{
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return -ENOSYS;
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}
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#endif /* CONFIG_VHOST */
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#endif
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