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virtio,pc,pci: features, cleanups
infrastructure for vhost-vdpa shadow work piix south bridge rework reconnect for vhost-user-scsi dummy ACPI QTG DSM for cxl tests, cleanups, fixes all over the place Signed-off-by: Michael S. Tsirkin <mst@redhat.com> -----BEGIN PGP SIGNATURE----- iQFDBAABCAAtFiEEXQn9CHHI+FuUyooNKB8NuNKNVGkFAmU06PMPHG1zdEByZWRo YXQuY29tAAoJECgfDbjSjVRpNIsH/0DlKti86VZLJ6PbNqsnKxoK2gg05TbEhPZU pQ+RPDaCHpFBsLC5qsoMJwvaEQFe0e49ZFemw7bXRzBxgmbbNnZ9ArCIPqT+rvQd 7UBmyC+kacVyybZatq69aK2BHKFtiIRlT78d9Izgtjmp8V7oyKoz14Esh8wkE+FT ypHUa70Addi6alNm6BVkm7bxZxi0Wrmf3THqF8ViYvufzHKl7JR5e17fKWEG0BqV 9W7AeHMnzJ7jkTvBGUw7g5EbzFn7hPLTbO4G/VW97k0puS4WRX5aIMkVhUazsRIa zDOuXCCskUWuRapiCwY0E4g7cCaT8/JR6JjjBaTgkjJgvo5Y8Eg= =ILek -----END PGP SIGNATURE----- Merge tag 'for_upstream' of https://git.kernel.org/pub/scm/virt/kvm/mst/qemu into staging virtio,pc,pci: features, cleanups infrastructure for vhost-vdpa shadow work piix south bridge rework reconnect for vhost-user-scsi dummy ACPI QTG DSM for cxl tests, cleanups, fixes all over the place Signed-off-by: Michael S. Tsirkin <mst@redhat.com> # -----BEGIN PGP SIGNATURE----- # # iQFDBAABCAAtFiEEXQn9CHHI+FuUyooNKB8NuNKNVGkFAmU06PMPHG1zdEByZWRo # YXQuY29tAAoJECgfDbjSjVRpNIsH/0DlKti86VZLJ6PbNqsnKxoK2gg05TbEhPZU # pQ+RPDaCHpFBsLC5qsoMJwvaEQFe0e49ZFemw7bXRzBxgmbbNnZ9ArCIPqT+rvQd # 7UBmyC+kacVyybZatq69aK2BHKFtiIRlT78d9Izgtjmp8V7oyKoz14Esh8wkE+FT # ypHUa70Addi6alNm6BVkm7bxZxi0Wrmf3THqF8ViYvufzHKl7JR5e17fKWEG0BqV # 9W7AeHMnzJ7jkTvBGUw7g5EbzFn7hPLTbO4G/VW97k0puS4WRX5aIMkVhUazsRIa # zDOuXCCskUWuRapiCwY0E4g7cCaT8/JR6JjjBaTgkjJgvo5Y8Eg= # =ILek # -----END PGP SIGNATURE----- # gpg: Signature made Sun 22 Oct 2023 02:18:43 PDT # gpg: using RSA key 5D09FD0871C8F85B94CA8A0D281F0DB8D28D5469 # gpg: issuer "mst@redhat.com" # gpg: Good signature from "Michael S. Tsirkin <mst@kernel.org>" [full] # gpg: aka "Michael S. Tsirkin <mst@redhat.com>" [full] # Primary key fingerprint: 0270 606B 6F3C DF3D 0B17 0970 C350 3912 AFBE 8E67 # Subkey fingerprint: 5D09 FD08 71C8 F85B 94CA 8A0D 281F 0DB8 D28D 5469 * tag 'for_upstream' of https://git.kernel.org/pub/scm/virt/kvm/mst/qemu: (62 commits) intel-iommu: Report interrupt remapping faults, fix return value MAINTAINERS: Add include/hw/intc/i8259.h to the PC chip section vhost-user: Fix protocol feature bit conflict tests/acpi: Update DSDT.cxl with QTG DSM hw/cxl: Add QTG _DSM support for ACPI0017 device tests/acpi: Allow update of DSDT.cxl hw/i386/cxl: ensure maxram is greater than ram size for calculating cxl range vhost-user: fix lost reconnect vhost-user-scsi: start vhost when guest kicks vhost-user-scsi: support reconnect to backend vhost: move and rename the conn retry times vhost-user-common: send get_inflight_fd once hw/i386/pc_piix: Make PIIX4 south bridge usable in PC machine hw/isa/piix: Implement multi-process QEMU support also for PIIX4 hw/isa/piix: Resolve duplicate code regarding PCI interrupt wiring hw/isa/piix: Reuse PIIX3's PCI interrupt triggering in PIIX4 hw/isa/piix: Rename functions to be shared for PCI interrupt triggering hw/isa/piix: Reuse PIIX3 base class' realize method in PIIX4 hw/isa/piix: Share PIIX3's base class with PIIX4 hw/isa/piix: Harmonize names of reset control memory regions ... Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
This commit is contained in:
Stefan Hajnoczi
commit
1b4a5a20da
43 changed files with 1218 additions and 836 deletions
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@ -469,21 +469,12 @@ static void vtd_set_frcd_and_update_ppf(IntelIOMMUState *s, uint16_t index)
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/* Must not update F field now, should be done later */
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static void vtd_record_frcd(IntelIOMMUState *s, uint16_t index,
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uint16_t source_id, hwaddr addr,
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VTDFaultReason fault, bool is_write,
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bool is_pasid, uint32_t pasid)
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uint64_t hi, uint64_t lo)
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{
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uint64_t hi = 0, lo;
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hwaddr frcd_reg_addr = DMAR_FRCD_REG_OFFSET + (((uint64_t)index) << 4);
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assert(index < DMAR_FRCD_REG_NR);
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lo = VTD_FRCD_FI(addr);
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hi = VTD_FRCD_SID(source_id) | VTD_FRCD_FR(fault) |
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VTD_FRCD_PV(pasid) | VTD_FRCD_PP(is_pasid);
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if (!is_write) {
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hi |= VTD_FRCD_T;
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}
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vtd_set_quad_raw(s, frcd_reg_addr, lo);
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vtd_set_quad_raw(s, frcd_reg_addr + 8, hi);
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@ -509,17 +500,11 @@ static bool vtd_try_collapse_fault(IntelIOMMUState *s, uint16_t source_id)
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}
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/* Log and report an DMAR (address translation) fault to software */
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static void vtd_report_dmar_fault(IntelIOMMUState *s, uint16_t source_id,
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hwaddr addr, VTDFaultReason fault,
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bool is_write, bool is_pasid,
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uint32_t pasid)
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static void vtd_report_frcd_fault(IntelIOMMUState *s, uint64_t source_id,
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uint64_t hi, uint64_t lo)
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{
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uint32_t fsts_reg = vtd_get_long_raw(s, DMAR_FSTS_REG);
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assert(fault < VTD_FR_MAX);
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trace_vtd_dmar_fault(source_id, fault, addr, is_write);
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if (fsts_reg & VTD_FSTS_PFO) {
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error_report_once("New fault is not recorded due to "
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"Primary Fault Overflow");
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@ -539,8 +524,7 @@ static void vtd_report_dmar_fault(IntelIOMMUState *s, uint16_t source_id,
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return;
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}
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vtd_record_frcd(s, s->next_frcd_reg, source_id, addr, fault,
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is_write, is_pasid, pasid);
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vtd_record_frcd(s, s->next_frcd_reg, hi, lo);
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if (fsts_reg & VTD_FSTS_PPF) {
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error_report_once("There are pending faults already, "
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@ -565,6 +549,40 @@ static void vtd_report_dmar_fault(IntelIOMMUState *s, uint16_t source_id,
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}
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}
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/* Log and report an DMAR (address translation) fault to software */
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static void vtd_report_dmar_fault(IntelIOMMUState *s, uint16_t source_id,
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hwaddr addr, VTDFaultReason fault,
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bool is_write, bool is_pasid,
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uint32_t pasid)
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{
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uint64_t hi, lo;
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assert(fault < VTD_FR_MAX);
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trace_vtd_dmar_fault(source_id, fault, addr, is_write);
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lo = VTD_FRCD_FI(addr);
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hi = VTD_FRCD_SID(source_id) | VTD_FRCD_FR(fault) |
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VTD_FRCD_PV(pasid) | VTD_FRCD_PP(is_pasid);
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if (!is_write) {
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hi |= VTD_FRCD_T;
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}
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vtd_report_frcd_fault(s, source_id, hi, lo);
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}
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static void vtd_report_ir_fault(IntelIOMMUState *s, uint64_t source_id,
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VTDFaultReason fault, uint16_t index)
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{
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uint64_t hi, lo;
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lo = VTD_FRCD_IR_IDX(index);
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hi = VTD_FRCD_SID(source_id) | VTD_FRCD_FR(fault);
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vtd_report_frcd_fault(s, source_id, hi, lo);
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}
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/* Handle Invalidation Queue Errors of queued invalidation interface error
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* conditions.
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*/
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@ -3305,8 +3323,9 @@ static Property vtd_properties[] = {
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};
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/* Read IRTE entry with specific index */
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static int vtd_irte_get(IntelIOMMUState *iommu, uint16_t index,
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VTD_IR_TableEntry *entry, uint16_t sid)
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static bool vtd_irte_get(IntelIOMMUState *iommu, uint16_t index,
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VTD_IR_TableEntry *entry, uint16_t sid,
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bool do_fault)
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{
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static const uint16_t vtd_svt_mask[VTD_SQ_MAX] = \
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{0xffff, 0xfffb, 0xfff9, 0xfff8};
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@ -3317,7 +3336,10 @@ static int vtd_irte_get(IntelIOMMUState *iommu, uint16_t index,
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if (index >= iommu->intr_size) {
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error_report_once("%s: index too large: ind=0x%x",
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__func__, index);
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return -VTD_FR_IR_INDEX_OVER;
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if (do_fault) {
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vtd_report_ir_fault(iommu, sid, VTD_FR_IR_INDEX_OVER, index);
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}
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return false;
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}
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addr = iommu->intr_root + index * sizeof(*entry);
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@ -3325,7 +3347,10 @@ static int vtd_irte_get(IntelIOMMUState *iommu, uint16_t index,
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entry, sizeof(*entry), MEMTXATTRS_UNSPECIFIED)) {
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error_report_once("%s: read failed: ind=0x%x addr=0x%" PRIx64,
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__func__, index, addr);
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return -VTD_FR_IR_ROOT_INVAL;
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if (do_fault) {
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vtd_report_ir_fault(iommu, sid, VTD_FR_IR_ROOT_INVAL, index);
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}
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return false;
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}
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entry->data[0] = le64_to_cpu(entry->data[0]);
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@ -3333,11 +3358,24 @@ static int vtd_irte_get(IntelIOMMUState *iommu, uint16_t index,
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trace_vtd_ir_irte_get(index, entry->data[1], entry->data[0]);
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/*
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* The remaining potential fault conditions are "qualified" by the
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* Fault Processing Disable bit in the IRTE. Even "not present".
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* So just clear the do_fault flag if PFD is set, which will
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* prevent faults being raised.
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*/
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if (entry->irte.fault_disable) {
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do_fault = false;
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}
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if (!entry->irte.present) {
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error_report_once("%s: detected non-present IRTE "
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"(index=%u, high=0x%" PRIx64 ", low=0x%" PRIx64 ")",
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__func__, index, entry->data[1], entry->data[0]);
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return -VTD_FR_IR_ENTRY_P;
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if (do_fault) {
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vtd_report_ir_fault(iommu, sid, VTD_FR_IR_ENTRY_P, index);
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}
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return false;
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}
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if (entry->irte.__reserved_0 || entry->irte.__reserved_1 ||
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@ -3345,7 +3383,10 @@ static int vtd_irte_get(IntelIOMMUState *iommu, uint16_t index,
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error_report_once("%s: detected non-zero reserved IRTE "
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"(index=%u, high=0x%" PRIx64 ", low=0x%" PRIx64 ")",
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__func__, index, entry->data[1], entry->data[0]);
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return -VTD_FR_IR_IRTE_RSVD;
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if (do_fault) {
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vtd_report_ir_fault(iommu, sid, VTD_FR_IR_IRTE_RSVD, index);
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}
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return false;
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}
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if (sid != X86_IOMMU_SID_INVALID) {
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@ -3361,7 +3402,10 @@ static int vtd_irte_get(IntelIOMMUState *iommu, uint16_t index,
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error_report_once("%s: invalid IRTE SID "
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"(index=%u, sid=%u, source_id=%u)",
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__func__, index, sid, source_id);
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return -VTD_FR_IR_SID_ERR;
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if (do_fault) {
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vtd_report_ir_fault(iommu, sid, VTD_FR_IR_SID_ERR, index);
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}
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return false;
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}
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break;
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@ -3373,7 +3417,10 @@ static int vtd_irte_get(IntelIOMMUState *iommu, uint16_t index,
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error_report_once("%s: invalid SVT_BUS "
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"(index=%u, bus=%u, min=%u, max=%u)",
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__func__, index, bus, bus_min, bus_max);
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return -VTD_FR_IR_SID_ERR;
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if (do_fault) {
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vtd_report_ir_fault(iommu, sid, VTD_FR_IR_SID_ERR, index);
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}
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return false;
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}
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break;
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@ -3382,23 +3429,24 @@ static int vtd_irte_get(IntelIOMMUState *iommu, uint16_t index,
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"(index=%u, type=%d)", __func__,
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index, entry->irte.sid_vtype);
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/* Take this as verification failure. */
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return -VTD_FR_IR_SID_ERR;
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if (do_fault) {
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vtd_report_ir_fault(iommu, sid, VTD_FR_IR_SID_ERR, index);
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}
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return false;
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}
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}
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return 0;
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return true;
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}
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/* Fetch IRQ information of specific IR index */
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static int vtd_remap_irq_get(IntelIOMMUState *iommu, uint16_t index,
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X86IOMMUIrq *irq, uint16_t sid)
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static bool vtd_remap_irq_get(IntelIOMMUState *iommu, uint16_t index,
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X86IOMMUIrq *irq, uint16_t sid, bool do_fault)
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{
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VTD_IR_TableEntry irte = {};
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int ret = 0;
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ret = vtd_irte_get(iommu, index, &irte, sid);
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if (ret) {
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return ret;
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if (!vtd_irte_get(iommu, index, &irte, sid, do_fault)) {
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return false;
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}
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irq->trigger_mode = irte.irte.trigger_mode;
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@ -3417,16 +3465,15 @@ static int vtd_remap_irq_get(IntelIOMMUState *iommu, uint16_t index,
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trace_vtd_ir_remap(index, irq->trigger_mode, irq->vector,
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irq->delivery_mode, irq->dest, irq->dest_mode);
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return 0;
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return true;
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}
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/* Interrupt remapping for MSI/MSI-X entry */
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static int vtd_interrupt_remap_msi(IntelIOMMUState *iommu,
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MSIMessage *origin,
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MSIMessage *translated,
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uint16_t sid)
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uint16_t sid, bool do_fault)
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{
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int ret = 0;
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VTD_IR_MSIAddress addr;
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uint16_t index;
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X86IOMMUIrq irq = {};
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@ -3443,14 +3490,20 @@ static int vtd_interrupt_remap_msi(IntelIOMMUState *iommu,
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if (origin->address & VTD_MSI_ADDR_HI_MASK) {
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error_report_once("%s: MSI address high 32 bits non-zero detected: "
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"address=0x%" PRIx64, __func__, origin->address);
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return -VTD_FR_IR_REQ_RSVD;
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if (do_fault) {
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vtd_report_ir_fault(iommu, sid, VTD_FR_IR_REQ_RSVD, 0);
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}
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return -EINVAL;
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}
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addr.data = origin->address & VTD_MSI_ADDR_LO_MASK;
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if (addr.addr.__head != 0xfee) {
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error_report_once("%s: MSI address low 32 bit invalid: 0x%" PRIx32,
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__func__, addr.data);
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return -VTD_FR_IR_REQ_RSVD;
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if (do_fault) {
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vtd_report_ir_fault(iommu, sid, VTD_FR_IR_REQ_RSVD, 0);
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}
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return -EINVAL;
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}
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/* This is compatible mode. */
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@ -3469,9 +3522,8 @@ static int vtd_interrupt_remap_msi(IntelIOMMUState *iommu,
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index += origin->data & VTD_IR_MSI_DATA_SUBHANDLE;
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}
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ret = vtd_remap_irq_get(iommu, index, &irq, sid);
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if (ret) {
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return ret;
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if (!vtd_remap_irq_get(iommu, index, &irq, sid, do_fault)) {
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return -EINVAL;
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}
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if (addr.addr.sub_valid) {
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@ -3481,7 +3533,10 @@ static int vtd_interrupt_remap_msi(IntelIOMMUState *iommu,
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"(sid=%u, address=0x%" PRIx64
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", data=0x%" PRIx32 ")",
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__func__, sid, origin->address, origin->data);
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return -VTD_FR_IR_REQ_RSVD;
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if (do_fault) {
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vtd_report_ir_fault(iommu, sid, VTD_FR_IR_REQ_RSVD, 0);
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}
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return -EINVAL;
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}
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} else {
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uint8_t vector = origin->data & 0xff;
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@ -3521,7 +3576,7 @@ static int vtd_int_remap(X86IOMMUState *iommu, MSIMessage *src,
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MSIMessage *dst, uint16_t sid)
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{
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return vtd_interrupt_remap_msi(INTEL_IOMMU_DEVICE(iommu),
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src, dst, sid);
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src, dst, sid, false);
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}
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static MemTxResult vtd_mem_ir_read(void *opaque, hwaddr addr,
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@ -3547,9 +3602,8 @@ static MemTxResult vtd_mem_ir_write(void *opaque, hwaddr addr,
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sid = attrs.requester_id;
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}
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ret = vtd_interrupt_remap_msi(opaque, &from, &to, sid);
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ret = vtd_interrupt_remap_msi(opaque, &from, &to, sid, true);
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if (ret) {
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/* TODO: report error */
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/* Drop this interrupt */
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return MEMTX_ERROR;
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}
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