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hw/intc: GICv3 ITS register definitions added

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Defined descriptors for ITS device table,collection table and ITS
command queue entities.Implemented register read/write functions,
extract ITS table parameters and command queue parameters,extended
gicv3 common to capture qemu address space(which host the ITS table
platform memories required for subsequent ITS processing) and
initialize the same in ITS device.

Signed-off-by: Shashi Mallela <shashi.mallela@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Tested-by: Neil Armstrong <narmstrong@baylibre.com>
Message-id: 20210910143951.92242-3-shashi.mallela@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Shashi Mallela 2021-09-13 16:07:23 +01:00 • committed by Peter Maydell
parent 18f6290a6a
commit 1b08e436d0
4 changed files with 431 additions and 0 deletions
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3
include/hw/intc/arm_gicv3_common.h
View file

@ -226,6 +226,9 @@ struct GICv3State {
int dev_fd; /* kvm device fd if backed by kvm vgic support */
Error *migration_blocker;
MemoryRegion *dma;
AddressSpace dma_as;
/* Distributor */
/* for a GIC with the security extensions the NS banked version of this

23
include/hw/intc/arm_gicv3_its_common.h
View file

@ -41,6 +41,25 @@
#define GITS_TRANSLATER 0x0040
typedef struct {
bool valid;
bool indirect;
uint16_t entry_sz;
uint32_t page_sz;
uint32_t max_entries;
union {
uint32_t max_devids;
uint32_t max_collids;
} maxids;
uint64_t base_addr;
} TableDesc;
typedef struct {
bool valid;
uint32_t max_entries;
uint64_t base_addr;
} CmdQDesc;
struct GICv3ITSState {
SysBusDevice parent_obj;
@ -63,6 +82,10 @@ struct GICv3ITSState {
uint64_t creadr;
uint64_t baser[8];
TableDesc dt;
TableDesc ct;
CmdQDesc cq;
Error *migration_blocker;
};