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target/arm: Use tcg_constant for gen_{msr,mrs}

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Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20220426163043.100432-25-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson 2022-04-26 09:30:20 -07:00 • committed by Peter Maydell
parent c49a6f0d52
commit 1a8598e038
1 changed files with 9 additions and 13 deletions
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22
target/arm/translate.c
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@ -2845,7 +2845,7 @@ static bool msr_banked_access_decode(DisasContext *s, int r, int sysm, int rn,
tcg_gen_sextract_i32(tcg_el, tcg_el, ctz32(SCR_EEL2), 1); tcg_gen_sextract_i32(tcg_el, tcg_el, ctz32(SCR_EEL2), 1);
tcg_gen_addi_i32(tcg_el, tcg_el, 3); tcg_gen_addi_i32(tcg_el, tcg_el, 3);
} else { } else {
tcg_el = tcg_const_i32(3); tcg_el = tcg_constant_i32(3);
} }
gen_exception_el(s, EXCP_UDEF, syn_uncategorized(), tcg_el); gen_exception_el(s, EXCP_UDEF, syn_uncategorized(), tcg_el);
@ -2880,7 +2880,7 @@ undef:
static void gen_msr_banked(DisasContext *s, int r, int sysm, int rn) static void gen_msr_banked(DisasContext *s, int r, int sysm, int rn)
{ {
TCGv_i32 tcg_reg, tcg_tgtmode, tcg_regno; TCGv_i32 tcg_reg;
int tgtmode = 0, regno = 0; int tgtmode = 0, regno = 0;
if (!msr_banked_access_decode(s, r, sysm, rn, &tgtmode, &regno)) { if (!msr_banked_access_decode(s, r, sysm, rn, &tgtmode, &regno)) {
@ -2891,18 +2891,16 @@ static void gen_msr_banked(DisasContext *s, int r, int sysm, int rn)
gen_set_condexec(s); gen_set_condexec(s);
gen_set_pc_im(s, s->pc_curr); gen_set_pc_im(s, s->pc_curr);
tcg_reg = load_reg(s, rn); tcg_reg = load_reg(s, rn);
tcg_tgtmode = tcg_const_i32(tgtmode); gen_helper_msr_banked(cpu_env, tcg_reg,
tcg_regno = tcg_const_i32(regno); tcg_constant_i32(tgtmode),
gen_helper_msr_banked(cpu_env, tcg_reg, tcg_tgtmode, tcg_regno); tcg_constant_i32(regno));
tcg_temp_free_i32(tcg_tgtmode);
tcg_temp_free_i32(tcg_regno);
tcg_temp_free_i32(tcg_reg); tcg_temp_free_i32(tcg_reg);
s->base.is_jmp = DISAS_UPDATE_EXIT; s->base.is_jmp = DISAS_UPDATE_EXIT;
} }
static void gen_mrs_banked(DisasContext *s, int r, int sysm, int rn) static void gen_mrs_banked(DisasContext *s, int r, int sysm, int rn)
{ {
TCGv_i32 tcg_reg, tcg_tgtmode, tcg_regno; TCGv_i32 tcg_reg;
int tgtmode = 0, regno = 0; int tgtmode = 0, regno = 0;
if (!msr_banked_access_decode(s, r, sysm, rn, &tgtmode, &regno)) { if (!msr_banked_access_decode(s, r, sysm, rn, &tgtmode, &regno)) {
@ -2913,11 +2911,9 @@ static void gen_mrs_banked(DisasContext *s, int r, int sysm, int rn)
gen_set_condexec(s); gen_set_condexec(s);
gen_set_pc_im(s, s->pc_curr); gen_set_pc_im(s, s->pc_curr);
tcg_reg = tcg_temp_new_i32(); tcg_reg = tcg_temp_new_i32();
tcg_tgtmode = tcg_const_i32(tgtmode); gen_helper_mrs_banked(tcg_reg, cpu_env,
tcg_regno = tcg_const_i32(regno); tcg_constant_i32(tgtmode),
gen_helper_mrs_banked(tcg_reg, cpu_env, tcg_tgtmode, tcg_regno); tcg_constant_i32(regno));
tcg_temp_free_i32(tcg_tgtmode);
tcg_temp_free_i32(tcg_regno);
store_reg(s, rn, tcg_reg); store_reg(s, rn, tcg_reg);
s->base.is_jmp = DISAS_UPDATE_EXIT; s->base.is_jmp = DISAS_UPDATE_EXIT;
} }