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target/riscv: remove cpu->cfg.ext_m

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Create a new "m" RISCVCPUMisaExtConfig property that will update
env->misa_ext* with RVM. Instances of cpu->cfg.ext_m and similar are
replaced with riscv_has_ext(env, RVM).

Remove the old "m" property and 'ext_m' from RISCVCPUConfig.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230406180351.570807-12-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Daniel Henrique Barboza 2023-04-06 15:03:42 -03:00 • committed by Alistair Francis
parent 427d8e7dd8
commit 1a36e23a62
2 changed files with 5 additions and 6 deletions
Download patch file Download diff file Expand all files Collapse all files

10
target/riscv/cpu.c
View file

@ -817,13 +817,13 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
CPURISCVState *env = &cpu->env; CPURISCVState *env = &cpu->env;
/* Do some ISA extension error checking */ /* Do some ISA extension error checking */
if (cpu->cfg.ext_g && !(riscv_has_ext(env, RVI) && cpu->cfg.ext_m && if (cpu->cfg.ext_g && !(riscv_has_ext(env, RVI) &&
riscv_has_ext(env, RVM) &&
riscv_has_ext(env, RVA) && riscv_has_ext(env, RVA) &&
riscv_has_ext(env, RVF) && riscv_has_ext(env, RVF) &&
riscv_has_ext(env, RVD) && riscv_has_ext(env, RVD) &&
cpu->cfg.ext_icsr && cpu->cfg.ext_ifencei)) { cpu->cfg.ext_icsr && cpu->cfg.ext_ifencei)) {
warn_report("Setting G will also set IMAFD_Zicsr_Zifencei"); warn_report("Setting G will also set IMAFD_Zicsr_Zifencei");
cpu->cfg.ext_m = true;
cpu->cfg.ext_icsr = true; cpu->cfg.ext_icsr = true;
cpu->cfg.ext_ifencei = true; cpu->cfg.ext_ifencei = true;
@ -1153,7 +1153,7 @@ static void riscv_cpu_sync_misa_cfg(CPURISCVState *env)
if (riscv_has_ext(env, RVE)) { if (riscv_has_ext(env, RVE)) {
ext |= RVE; ext |= RVE;
} }
if (riscv_cpu_cfg(env)->ext_m) { if (riscv_has_ext(env, RVM)) {
ext |= RVM; ext |= RVM;
} }
if (riscv_has_ext(env, RVA)) { if (riscv_has_ext(env, RVA)) {
@ -1505,6 +1505,8 @@ static const RISCVCPUMisaExtConfig misa_ext_cfgs[] = {
.misa_bit = RVI, .enabled = true}, .misa_bit = RVI, .enabled = true},
{.name = "e", .description = "Base integer instruction set (embedded)", {.name = "e", .description = "Base integer instruction set (embedded)",
.misa_bit = RVE, .enabled = false}, .misa_bit = RVE, .enabled = false},
{.name = "m", .description = "Integer multiplication and division",
.misa_bit = RVM, .enabled = true},
}; };
static void riscv_cpu_add_misa_properties(Object *cpu_obj) static void riscv_cpu_add_misa_properties(Object *cpu_obj)
@ -1528,7 +1530,6 @@ static void riscv_cpu_add_misa_properties(Object *cpu_obj)
static Property riscv_cpu_extensions[] = { static Property riscv_cpu_extensions[] = {
/* Defaults for standard extensions */ /* Defaults for standard extensions */
DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, false), DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, false),
DEFINE_PROP_BOOL("m", RISCVCPU, cfg.ext_m, true),
DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true), DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true),
DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true), DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true),
DEFINE_PROP_BOOL("v", RISCVCPU, cfg.ext_v, false), DEFINE_PROP_BOOL("v", RISCVCPU, cfg.ext_v, false),
@ -1645,7 +1646,6 @@ static void register_cpu_props(Object *obj)
* later on. * later on.
*/ */
if (cpu->env.misa_ext != 0) { if (cpu->env.misa_ext != 0) {
cpu->cfg.ext_m = misa_ext & RVM;
cpu->cfg.ext_v = misa_ext & RVV; cpu->cfg.ext_v = misa_ext & RVV;
cpu->cfg.ext_s = misa_ext & RVS; cpu->cfg.ext_s = misa_ext & RVS;
cpu->cfg.ext_u = misa_ext & RVU; cpu->cfg.ext_u = misa_ext & RVU;

1
target/riscv/cpu.h
View file

@ -423,7 +423,6 @@ typedef struct {
struct RISCVCPUConfig { struct RISCVCPUConfig {
bool ext_g; bool ext_g;
bool ext_m;
bool ext_s; bool ext_s;
bool ext_u; bool ext_u;
bool ext_h; bool ext_h;