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Avoid address_space_rw() with a constant is_write argument
The address_space_rw() function allows either reads or writes depending on the is_write argument passed to it; this is useful when the direction of the access is determined programmatically (as for instance when handling the KVM_EXIT_MMIO exit reason). Under the hood it just calls either address_space_write() or address_space_read_full(). We also use it a lot with a constant is_write argument, though, which has two issues: * when reading "address_space_rw(..., 1)" this is less immediately clear to the reader as being a write than "address_space_write(...)" * calling address_space_rw() bypasses the optimization in address_space_read() that fast-paths reads of a fixed length This commit was produced with the included Coccinelle script scripts/coccinelle/exec_rw_const.cocci. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Laurent Vivier <lvivier@redhat.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Acked-by: Christian Borntraeger <borntraeger@de.ibm.com> Reviewed-by: Cornelia Huck <cohuck@redhat.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Acked-by: David Gibson <david@gibson.dropbear.id.au> Message-Id: <20200218112457.22712-1-peter.maydell@linaro.org> [PMD: Update macvm_set_cr0() reported by Laurent Vivier] Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
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13 changed files with 119 additions and 107 deletions
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@ -125,10 +125,9 @@ static inline void macvm_set_cr0(hv_vcpuid_t vcpu, uint64_t cr0)
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if ((cr0 & CR0_PG) && (rvmcs(vcpu, VMCS_GUEST_CR4) & CR4_PAE) &&
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!(efer & MSR_EFER_LME)) {
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address_space_rw(&address_space_memory,
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rvmcs(vcpu, VMCS_GUEST_CR3) & ~0x1f,
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MEMTXATTRS_UNSPECIFIED,
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pdpte, 32, false);
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address_space_read(&address_space_memory,
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rvmcs(vcpu, VMCS_GUEST_CR3) & ~0x1f,
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MEMTXATTRS_UNSPECIFIED, pdpte, 32);
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/* Only set PDPTE when appropriate. */
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for (i = 0; i < 4; i++) {
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wvmcs(vcpu, VMCS_GUEST_PDPTE0 + i * 2, pdpte[i]);
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@ -88,8 +88,8 @@ static bool get_pt_entry(struct CPUState *cpu, struct gpt_translation *pt,
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}
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index = gpt_entry(pt->gva, level, pae);
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address_space_rw(&address_space_memory, gpa + index * pte_size(pae),
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MEMTXATTRS_UNSPECIFIED, &pte, pte_size(pae), false);
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address_space_read(&address_space_memory, gpa + index * pte_size(pae),
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MEMTXATTRS_UNSPECIFIED, &pte, pte_size(pae));
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pt->pte[level - 1] = pte;
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@ -238,8 +238,8 @@ void vmx_write_mem(struct CPUState *cpu, target_ulong gva, void *data, int bytes
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if (!mmu_gva_to_gpa(cpu, gva, &gpa)) {
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VM_PANIC_EX("%s: mmu_gva_to_gpa %llx failed\n", __func__, gva);
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} else {
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address_space_rw(&address_space_memory, gpa,
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MEMTXATTRS_UNSPECIFIED, data, copy, true);
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address_space_write(&address_space_memory, gpa,
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MEMTXATTRS_UNSPECIFIED, data, copy);
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}
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bytes -= copy;
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@ -259,8 +259,8 @@ void vmx_read_mem(struct CPUState *cpu, void *data, target_ulong gva, int bytes)
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if (!mmu_gva_to_gpa(cpu, gva, &gpa)) {
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VM_PANIC_EX("%s: mmu_gva_to_gpa %llx failed\n", __func__, gva);
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}
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address_space_rw(&address_space_memory, gpa, MEMTXATTRS_UNSPECIFIED,
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data, copy, false);
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address_space_read(&address_space_memory, gpa, MEMTXATTRS_UNSPECIFIED,
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data, copy);
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bytes -= copy;
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gva += copy;
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