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Avoid address_space_rw() with a constant is_write argument
The address_space_rw() function allows either reads or writes depending on the is_write argument passed to it; this is useful when the direction of the access is determined programmatically (as for instance when handling the KVM_EXIT_MMIO exit reason). Under the hood it just calls either address_space_write() or address_space_read_full(). We also use it a lot with a constant is_write argument, though, which has two issues: * when reading "address_space_rw(..., 1)" this is less immediately clear to the reader as being a write than "address_space_write(...)" * calling address_space_rw() bypasses the optimization in address_space_read() that fast-paths reads of a fixed length This commit was produced with the included Coccinelle script scripts/coccinelle/exec_rw_const.cocci. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Laurent Vivier <lvivier@redhat.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Acked-by: Christian Borntraeger <borntraeger@de.ibm.com> Reviewed-by: Cornelia Huck <cohuck@redhat.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Acked-by: David Gibson <david@gibson.dropbear.id.au> Message-Id: <20200218112457.22712-1-peter.maydell@linaro.org> [PMD: Update macvm_set_cr0() reported by Laurent Vivier] Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
This commit is contained in:
Peter Maydell
Philippe Mathieu-Daudé
parent
1ccda935d4
commit
19f7034773
13 changed files with 119 additions and 107 deletions
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@ -311,8 +311,7 @@ static bool zdma_load_descriptor(XlnxZDMA *s, uint64_t addr, void *buf)
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return false;
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}
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address_space_rw(s->dma_as, addr, s->attr,
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buf, sizeof(XlnxZDMADescr), false);
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address_space_read(s->dma_as, addr, s->attr, buf, sizeof(XlnxZDMADescr));
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return true;
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}
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@ -364,7 +363,7 @@ static uint64_t zdma_update_descr_addr(XlnxZDMA *s, bool type,
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} else {
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addr = zdma_get_regaddr64(s, basereg);
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addr += sizeof(s->dsc_dst);
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address_space_rw(s->dma_as, addr, s->attr, &next, 8, false);
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address_space_read(s->dma_as, addr, s->attr, &next, 8);
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zdma_put_regaddr64(s, basereg, next);
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}
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return next;
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@ -416,8 +415,7 @@ static void zdma_write_dst(XlnxZDMA *s, uint8_t *buf, uint32_t len)
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}
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}
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address_space_rw(s->dma_as, s->dsc_dst.addr, s->attr, buf, dlen,
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true);
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address_space_write(s->dma_as, s->dsc_dst.addr, s->attr, buf, dlen);
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if (burst_type == AXI_BURST_INCR) {
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s->dsc_dst.addr += dlen;
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}
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@ -493,8 +491,7 @@ static void zdma_process_descr(XlnxZDMA *s)
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len = s->cfg.bus_width / 8;
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}
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} else {
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address_space_rw(s->dma_as, src_addr, s->attr, s->buf, len,
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false);
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address_space_read(s->dma_as, src_addr, s->attr, s->buf, len);
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if (burst_type == AXI_BURST_INCR) {
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src_addr += len;
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}
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@ -275,8 +275,8 @@ static void dp8393x_do_load_cam(dp8393xState *s)
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while (s->regs[SONIC_CDC] & 0x1f) {
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/* Fill current entry */
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address_space_rw(&s->as, dp8393x_cdp(s),
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MEMTXATTRS_UNSPECIFIED, s->data, size, false);
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address_space_read(&s->as, dp8393x_cdp(s),
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MEMTXATTRS_UNSPECIFIED, s->data, size);
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s->cam[index][0] = dp8393x_get(s, width, 1) & 0xff;
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s->cam[index][1] = dp8393x_get(s, width, 1) >> 8;
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s->cam[index][2] = dp8393x_get(s, width, 2) & 0xff;
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@ -293,8 +293,8 @@ static void dp8393x_do_load_cam(dp8393xState *s)
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}
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/* Read CAM enable */
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address_space_rw(&s->as, dp8393x_cdp(s),
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MEMTXATTRS_UNSPECIFIED, s->data, size, false);
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address_space_read(&s->as, dp8393x_cdp(s),
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MEMTXATTRS_UNSPECIFIED, s->data, size);
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s->regs[SONIC_CE] = dp8393x_get(s, width, 0);
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DPRINTF("load cam done. cam enable mask 0x%04x\n", s->regs[SONIC_CE]);
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@ -311,8 +311,8 @@ static void dp8393x_do_read_rra(dp8393xState *s)
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/* Read memory */
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width = (s->regs[SONIC_DCR] & SONIC_DCR_DW) ? 2 : 1;
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size = sizeof(uint16_t) * 4 * width;
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address_space_rw(&s->as, dp8393x_rrp(s),
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MEMTXATTRS_UNSPECIFIED, s->data, size, false);
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address_space_read(&s->as, dp8393x_rrp(s),
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MEMTXATTRS_UNSPECIFIED, s->data, size);
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/* Update SONIC registers */
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s->regs[SONIC_CRBA0] = dp8393x_get(s, width, 0);
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@ -426,8 +426,8 @@ static void dp8393x_do_transmit_packets(dp8393xState *s)
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size = sizeof(uint16_t) * 6 * width;
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s->regs[SONIC_TTDA] = s->regs[SONIC_CTDA];
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DPRINTF("Transmit packet at %08x\n", dp8393x_ttda(s));
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address_space_rw(&s->as, dp8393x_ttda(s) + sizeof(uint16_t) * width,
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MEMTXATTRS_UNSPECIFIED, s->data, size, false);
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address_space_read(&s->as, dp8393x_ttda(s) + sizeof(uint16_t) * width,
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MEMTXATTRS_UNSPECIFIED, s->data, size);
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tx_len = 0;
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/* Update registers */
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@ -451,18 +451,19 @@ static void dp8393x_do_transmit_packets(dp8393xState *s)
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if (tx_len + len > sizeof(s->tx_buffer)) {
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len = sizeof(s->tx_buffer) - tx_len;
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}
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address_space_rw(&s->as, dp8393x_tsa(s),
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MEMTXATTRS_UNSPECIFIED,
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&s->tx_buffer[tx_len], len, false);
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address_space_read(&s->as, dp8393x_tsa(s), MEMTXATTRS_UNSPECIFIED,
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&s->tx_buffer[tx_len], len);
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tx_len += len;
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i++;
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if (i != s->regs[SONIC_TFC]) {
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/* Read next fragment details */
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size = sizeof(uint16_t) * 3 * width;
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address_space_rw(&s->as,
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dp8393x_ttda(s) + sizeof(uint16_t) * (4 + 3 * i) * width,
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MEMTXATTRS_UNSPECIFIED, s->data, size, false);
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address_space_read(&s->as,
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dp8393x_ttda(s)
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+ sizeof(uint16_t) * width * (4 + 3 * i),
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MEMTXATTRS_UNSPECIFIED, s->data,
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size);
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s->regs[SONIC_TSA0] = dp8393x_get(s, width, 0);
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s->regs[SONIC_TSA1] = dp8393x_get(s, width, 1);
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s->regs[SONIC_TFS] = dp8393x_get(s, width, 2);
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@ -495,18 +496,18 @@ static void dp8393x_do_transmit_packets(dp8393xState *s)
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dp8393x_put(s, width, 0,
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s->regs[SONIC_TCR] & 0x0fff); /* status */
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size = sizeof(uint16_t) * width;
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address_space_rw(&s->as,
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dp8393x_ttda(s),
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MEMTXATTRS_UNSPECIFIED, s->data, size, true);
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address_space_write(&s->as, dp8393x_ttda(s),
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MEMTXATTRS_UNSPECIFIED, s->data, size);
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if (!(s->regs[SONIC_CR] & SONIC_CR_HTX)) {
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/* Read footer of packet */
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size = sizeof(uint16_t) * width;
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address_space_rw(&s->as,
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dp8393x_ttda(s) +
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sizeof(uint16_t) *
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(4 + 3 * s->regs[SONIC_TFC]) * width,
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MEMTXATTRS_UNSPECIFIED, s->data, size, false);
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address_space_read(&s->as,
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dp8393x_ttda(s)
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+ sizeof(uint16_t) * width
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* (4 + 3 * s->regs[SONIC_TFC]),
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MEMTXATTRS_UNSPECIFIED, s->data,
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size);
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s->regs[SONIC_CTDA] = dp8393x_get(s, width, 0) & ~0x1;
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if (dp8393x_get(s, width, 0) & 0x1) {
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/* EOL detected */
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@ -768,8 +769,8 @@ static ssize_t dp8393x_receive(NetClientState *nc, const uint8_t * buf,
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/* Are we still in resource exhaustion? */
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size = sizeof(uint16_t) * 1 * width;
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address = dp8393x_crda(s) + sizeof(uint16_t) * 5 * width;
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address_space_rw(&s->as, address, MEMTXATTRS_UNSPECIFIED,
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s->data, size, false);
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address_space_read(&s->as, address, MEMTXATTRS_UNSPECIFIED,
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s->data, size);
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if (dp8393x_get(s, width, 0) & 0x1) {
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/* Still EOL ; stop reception */
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return -1;
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@ -788,10 +789,11 @@ static ssize_t dp8393x_receive(NetClientState *nc, const uint8_t * buf,
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/* Put packet into RBA */
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DPRINTF("Receive packet at %08x\n", dp8393x_crba(s));
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address = dp8393x_crba(s);
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address_space_write(&s->as, address, MEMTXATTRS_UNSPECIFIED, buf, rx_len);
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address_space_write(&s->as, address, MEMTXATTRS_UNSPECIFIED,
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buf, rx_len);
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address += rx_len;
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address_space_rw(&s->as, address,
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MEMTXATTRS_UNSPECIFIED, &checksum, 4, true);
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address_space_write(&s->as, address, MEMTXATTRS_UNSPECIFIED,
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&checksum, 4);
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rx_len += 4;
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s->regs[SONIC_CRBA1] = address >> 16;
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s->regs[SONIC_CRBA0] = address & 0xffff;
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@ -819,13 +821,15 @@ static ssize_t dp8393x_receive(NetClientState *nc, const uint8_t * buf,
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dp8393x_put(s, width, 3, s->regs[SONIC_TRBA1]); /* pkt_ptr1 */
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dp8393x_put(s, width, 4, s->regs[SONIC_RSC]); /* seq_no */
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size = sizeof(uint16_t) * 5 * width;
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address_space_rw(&s->as, dp8393x_crda(s),
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MEMTXATTRS_UNSPECIFIED, s->data, size, true);
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address_space_write(&s->as, dp8393x_crda(s),
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MEMTXATTRS_UNSPECIFIED,
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s->data, size);
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/* Move to next descriptor */
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size = sizeof(uint16_t) * width;
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address_space_rw(&s->as, dp8393x_crda(s) + sizeof(uint16_t) * 5 * width,
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MEMTXATTRS_UNSPECIFIED, s->data, size, false);
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address_space_read(&s->as,
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dp8393x_crda(s) + sizeof(uint16_t) * 5 * width,
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MEMTXATTRS_UNSPECIFIED, s->data, size);
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s->regs[SONIC_LLFA] = dp8393x_get(s, width, 0);
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if (s->regs[SONIC_LLFA] & 0x1) {
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/* EOL detected */
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@ -838,8 +842,8 @@ static ssize_t dp8393x_receive(NetClientState *nc, const uint8_t * buf,
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offset += sizeof(uint16_t);
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}
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s->data[0] = 0;
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address_space_rw(&s->as, offset, MEMTXATTRS_UNSPECIFIED,
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s->data, sizeof(uint16_t), true);
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address_space_write(&s->as, offset, MEMTXATTRS_UNSPECIFIED,
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s->data, sizeof(uint16_t));
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s->regs[SONIC_CRDA] = s->regs[SONIC_LLFA];
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s->regs[SONIC_ISR] |= SONIC_ISR_PKTRX;
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s->regs[SONIC_RSC] = (s->regs[SONIC_RSC] & 0xff00) | (((s->regs[SONIC_RSC] & 0x00ff) + 1) & 0x00ff);
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@ -148,8 +148,8 @@ static void i82596_transmit(I82596State *s, uint32_t addr)
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if (s->nic && len) {
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assert(len <= sizeof(s->tx_buffer));
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address_space_rw(&address_space_memory, tba,
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MEMTXATTRS_UNSPECIFIED, s->tx_buffer, len, false);
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address_space_read(&address_space_memory, tba,
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MEMTXATTRS_UNSPECIFIED, s->tx_buffer, len);
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DBG(PRINT_PKTHDR("Send", &s->tx_buffer));
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DBG(printf("Sending %d bytes\n", len));
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qemu_send_packet(qemu_get_queue(s->nic), s->tx_buffer, len);
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@ -172,8 +172,8 @@ static void set_individual_address(I82596State *s, uint32_t addr)
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nc = qemu_get_queue(s->nic);
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m = s->conf.macaddr.a;
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address_space_rw(&address_space_memory, addr + 8,
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MEMTXATTRS_UNSPECIFIED, m, ETH_ALEN, false);
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address_space_read(&address_space_memory, addr + 8,
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MEMTXATTRS_UNSPECIFIED, m, ETH_ALEN);
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qemu_format_nic_info_str(nc, m);
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trace_i82596_new_mac(nc->info_str);
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}
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@ -190,9 +190,8 @@ static void set_multicast_list(I82596State *s, uint32_t addr)
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}
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for (i = 0; i < mc_count; i++) {
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uint8_t multicast_addr[ETH_ALEN];
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address_space_rw(&address_space_memory,
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addr + i * ETH_ALEN, MEMTXATTRS_UNSPECIFIED,
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multicast_addr, ETH_ALEN, false);
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address_space_read(&address_space_memory, addr + i * ETH_ALEN,
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MEMTXATTRS_UNSPECIFIED, multicast_addr, ETH_ALEN);
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DBG(printf("Add multicast entry " MAC_FMT "\n",
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MAC_ARG(multicast_addr)));
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unsigned mcast_idx = (net_crc32(multicast_addr, ETH_ALEN) &
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@ -260,9 +259,8 @@ static void command_loop(I82596State *s)
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byte_cnt = MAX(byte_cnt, 4);
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byte_cnt = MIN(byte_cnt, sizeof(s->config));
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/* copy byte_cnt max. */
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address_space_rw(&address_space_memory, s->cmd_p + 8,
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MEMTXATTRS_UNSPECIFIED, s->config, byte_cnt,
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false);
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address_space_read(&address_space_memory, s->cmd_p + 8,
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MEMTXATTRS_UNSPECIFIED, s->config, byte_cnt);
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/* config byte according to page 35ff */
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s->config[2] &= 0x82; /* mask valid bits */
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s->config[2] |= 0x40;
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@ -647,8 +645,8 @@ ssize_t i82596_receive(NetClientState *nc, const uint8_t *buf, size_t sz)
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buf += num;
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len -= num;
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if (len == 0) { /* copy crc */
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address_space_rw(&address_space_memory, rba - 4,
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MEMTXATTRS_UNSPECIFIED, crc_ptr, 4, true);
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address_space_write(&address_space_memory, rba - 4,
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MEMTXATTRS_UNSPECIFIED, crc_ptr, 4);
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}
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num |= 0x4000; /* set F BIT */
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@ -55,8 +55,9 @@ static void lasi_82596_mem_write(void *opaque, hwaddr addr,
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* Provided for SeaBIOS only. Write MAC of Network card to addr @val.
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* Needed for the PDC_LAN_STATION_ID_READ PDC call.
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*/
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address_space_rw(&address_space_memory, val, MEMTXATTRS_UNSPECIFIED,
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d->state.conf.macaddr.a, ETH_ALEN, true);
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address_space_write(&address_space_memory, val,
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MEMTXATTRS_UNSPECIFIED, d->state.conf.macaddr.a,
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ETH_ALEN);
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break;
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}
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}
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@ -238,16 +238,16 @@ static bool opb_read(PnvLpcController *lpc, uint32_t addr, uint8_t *data,
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int sz)
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{
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/* XXX Handle access size limits and FW read caching here */
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return !address_space_rw(&lpc->opb_as, addr, MEMTXATTRS_UNSPECIFIED,
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data, sz, false);
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return !address_space_read(&lpc->opb_as, addr, MEMTXATTRS_UNSPECIFIED,
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data, sz);
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}
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static bool opb_write(PnvLpcController *lpc, uint32_t addr, uint8_t *data,
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int sz)
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{
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/* XXX Handle access size limits here */
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return !address_space_rw(&lpc->opb_as, addr, MEMTXATTRS_UNSPECIFIED,
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data, sz, true);
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return !address_space_write(&lpc->opb_as, addr, MEMTXATTRS_UNSPECIFIED,
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data, sz);
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}
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#define ECCB_CTL_READ PPC_BIT(15)
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@ -874,18 +874,18 @@ static inline int ida_read_next_idaw(CcwDataStream *cds)
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if (idaw_addr & 0x07 || !cds_ccw_addrs_ok(idaw_addr, 0, ccw_fmt1)) {
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return -EINVAL; /* channel program check */
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}
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ret = address_space_rw(&address_space_memory, idaw_addr,
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MEMTXATTRS_UNSPECIFIED, &idaw.fmt2,
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sizeof(idaw.fmt2), false);
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ret = address_space_read(&address_space_memory, idaw_addr,
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MEMTXATTRS_UNSPECIFIED, &idaw.fmt2,
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sizeof(idaw.fmt2));
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cds->cda = be64_to_cpu(idaw.fmt2);
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} else {
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idaw_addr = cds->cda_orig + sizeof(idaw.fmt1) * cds->at_idaw;
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if (idaw_addr & 0x03 || !cds_ccw_addrs_ok(idaw_addr, 0, ccw_fmt1)) {
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return -EINVAL; /* channel program check */
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}
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ret = address_space_rw(&address_space_memory, idaw_addr,
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MEMTXATTRS_UNSPECIFIED, &idaw.fmt1,
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sizeof(idaw.fmt1), false);
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ret = address_space_read(&address_space_memory, idaw_addr,
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MEMTXATTRS_UNSPECIFIED, &idaw.fmt1,
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sizeof(idaw.fmt1));
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cds->cda = be64_to_cpu(idaw.fmt1);
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if (cds->cda & 0x80000000) {
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return -EINVAL; /* channel program check */
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