motorhead/qemu
1
0
Fork 0
mirror of https://github.com/Motorhead1991/qemu.git synced 2025-08-02 23:33:54 -06:00
Code Issues Projects Releases Packages Wiki Activity Actions

target-mips: Fix incorrect shift for SHILO and SHILOV

Browse source 
helper_shilo has not been shifting an accumulator value correctly for negative
values in 'shift' field. Minor optimization for shift=0 case.
This change also adds tests that will trigger issue and check for regressions.

Signed-off-by: Petar Jovanovic <petarj@mips.com>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Reviewed-by: Eric Johnson <ericj@mips.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
This commit is contained in:
Petar Jovanovic 2012-12-05 00:29:10 +01:00 • committed by Aurelien Jarno
parent 34f5606ee1
commit 19e6c50d2d
3 changed files with 47 additions and 8 deletions
Download patch file Download diff file Expand all files Collapse all files

17
target-mips/dsp_helper.c
View file

@ -3814,17 +3814,18 @@ void helper_shilo(target_ulong ac, target_ulong rs, CPUMIPSState *env)
rs5_0 = rs & 0x3F;
rs5_0 = (int8_t)(rs5_0 << 2) >> 2;
rs5_0 = MIPSDSP_ABS(rs5_0);
if (unlikely(rs5_0 == 0)) {
return;
}
acc = (((uint64_t)env->active_tc.HI[ac] << 32) & MIPSDSP_LHI) |
((uint64_t)env->active_tc.LO[ac] & MIPSDSP_LLO);
if (rs5_0 == 0) {
temp = acc;
if (rs5_0 > 0) {
temp = acc >> rs5_0;
} else {
if (rs5_0 > 0) {
temp = acc >> rs5_0;
} else {
temp = acc << rs5_0;
}
temp = acc << -rs5_0;
}
env->active_tc.HI[ac] = (target_ulong)(int32_t)((temp & MIPSDSP_LHI) >> 32);