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target/arm: Enable FEAT_XS for the max cpu

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Add FEAT_XS feature report value in max cpu's ID_AA64ISAR1 sys register.

Signed-off-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241211144440.2700268-6-peter.maydell@linaro.org
[PMM: Add entry for FEAT_XS to documentation]
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Manos Pitsidianakis 2024-12-11 14:44:39 +00:00 • committed by Peter Maydell
parent a65a24b9cf
commit 19db1d4da7
2 changed files with 2 additions and 0 deletions
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1
docs/system/arm/emulation.rst
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@ -154,6 +154,7 @@ the following architecture extensions:
- FEAT_VMID16 (16-bit VMID) - FEAT_VMID16 (16-bit VMID)
- FEAT_WFxT (WFE and WFI instructions with timeout) - FEAT_WFxT (WFE and WFI instructions with timeout)
- FEAT_XNX (Translation table stage 2 Unprivileged Execute-never) - FEAT_XNX (Translation table stage 2 Unprivileged Execute-never)
- FEAT_XS (XS attribute)
For information on the specifics of these extensions, please refer For information on the specifics of these extensions, please refer
to the `Arm Architecture Reference Manual for A-profile architecture to the `Arm Architecture Reference Manual for A-profile architecture

1
target/arm/tcg/cpu64.c
View file

@ -1163,6 +1163,7 @@ void aarch64_max_tcg_initfn(Object *obj)
t = FIELD_DP64(t, ID_AA64ISAR1, BF16, 2); /* FEAT_BF16, FEAT_EBF16 */ t = FIELD_DP64(t, ID_AA64ISAR1, BF16, 2); /* FEAT_BF16, FEAT_EBF16 */
t = FIELD_DP64(t, ID_AA64ISAR1, DGH, 1); /* FEAT_DGH */ t = FIELD_DP64(t, ID_AA64ISAR1, DGH, 1); /* FEAT_DGH */
t = FIELD_DP64(t, ID_AA64ISAR1, I8MM, 1); /* FEAT_I8MM */ t = FIELD_DP64(t, ID_AA64ISAR1, I8MM, 1); /* FEAT_I8MM */
t = FIELD_DP64(t, ID_AA64ISAR1, XS, 1); /* FEAT_XS */
cpu->isar.id_aa64isar1 = t; cpu->isar.id_aa64isar1 = t;
t = cpu->isar.id_aa64isar2; t = cpu->isar.id_aa64isar2;