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hw/pci-bridge: Constify all Property

Browse source 
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2024-12-13 16:32:51 +00:00
parent 2839136833
commit 196fd15f31
9 changed files with 10 additions and 10 deletions
Download patch file Download diff file Expand all files Collapse all files

2
hw/pci-bridge/cxl_downstream.c
View file

@ -212,7 +212,7 @@ static void cxl_dsp_exitfn(PCIDevice *d)
pci_bridge_exitfn(d);
}
static Property cxl_dsp_props[] = {
static const Property cxl_dsp_props[] = {
DEFINE_PROP_PCIE_LINK_SPEED("x-speed", PCIESlot,
speed, PCIE_LINK_SPEED_64),
DEFINE_PROP_PCIE_LINK_WIDTH("x-width", PCIESlot,

2
hw/pci-bridge/cxl_root_port.c
View file

@ -199,7 +199,7 @@ static void cxl_rp_reset_hold(Object *obj, ResetType type)
latch_registers(crp);
}
static Property gen_rp_props[] = {
static const Property gen_rp_props[] = {
DEFINE_PROP_UINT32("bus-reserve", CXLRootPort, res_reserve.bus, -1),
DEFINE_PROP_SIZE("io-reserve", CXLRootPort, res_reserve.io, -1),
DEFINE_PROP_SIZE("mem-reserve", CXLRootPort, res_reserve.mem_non_pref, -1),

2
hw/pci-bridge/cxl_upstream.c
View file

@ -362,7 +362,7 @@ static void cxl_usp_exitfn(PCIDevice *d)
pci_bridge_exitfn(d);
}
static Property cxl_upstream_props[] = {
static const Property cxl_upstream_props[] = {
DEFINE_PROP_UINT64("sn", CXLUpstreamPort, sn, UI64_NULL),
DEFINE_PROP_STRING("cdat", CXLUpstreamPort, cxl_cstate.cdat.filename),
DEFINE_PROP_PCIE_LINK_SPEED("x-speed", CXLUpstreamPort,

2
hw/pci-bridge/gen_pcie_root_port.c
View file

@ -128,7 +128,7 @@ static const VMStateDescription vmstate_rp_dev = {
}
};
static Property gen_rp_props[] = {
static const Property gen_rp_props[] = {
DEFINE_PROP_BOOL("x-migrate-msix", GenPCIERootPort,
migrate_msix, true),
DEFINE_PROP_UINT32("bus-reserve", GenPCIERootPort,

2
hw/pci-bridge/pci_bridge_dev.c
View file

@ -168,7 +168,7 @@ static void qdev_pci_bridge_dev_reset(DeviceState *qdev)
}
}
static Property pci_bridge_dev_properties[] = {
static const Property pci_bridge_dev_properties[] = {
/* Note: 0 is not a legal chassis number. */
DEFINE_PROP_UINT8(PCI_BRIDGE_DEV_PROP_CHASSIS_NR, PCIBridgeDev, chassis_nr,
0),

4
hw/pci-bridge/pci_expander_bridge.c
View file

@ -420,7 +420,7 @@ static void pxb_dev_exitfn(PCIDevice *pci_dev)
pxb_dev_list = g_list_remove(pxb_dev_list, pxb);
}
static Property pxb_dev_properties[] = {
static const Property pxb_dev_properties[] = {
/* Note: 0 is not a legal PXB bus number. */
DEFINE_PROP_UINT8("bus_nr", PXBDev, bus_nr, 0),
DEFINE_PROP_UINT16("numa_node", PXBDev, numa_node, NUMA_NODE_UNASSIGNED),
@ -507,7 +507,7 @@ static void pxb_cxl_dev_realize(PCIDevice *dev, Error **errp)
pxb_cxl_dev_reset(DEVICE(dev));
}
static Property pxb_cxl_dev_properties[] = {
static const Property pxb_cxl_dev_properties[] = {
DEFINE_PROP_BOOL("hdm_for_passthrough", PXBCXLDev, hdm_for_passthrough, false),
DEFINE_PROP_END_OF_LIST(),
};

2
hw/pci-bridge/pcie_pci_bridge.c
View file

@ -124,7 +124,7 @@ static void pcie_pci_bridge_write_config(PCIDevice *d,
shpc_cap_write_config(d, address, val, len);
}
static Property pcie_pci_bridge_dev_properties[] = {
static const Property pcie_pci_bridge_dev_properties[] = {
DEFINE_PROP_ON_OFF_AUTO("msi", PCIEPCIBridge, msi, ON_OFF_AUTO_AUTO),
DEFINE_PROP_END_OF_LIST(),
};

2
hw/pci-bridge/pcie_root_port.c
View file

@ -148,7 +148,7 @@ static void rp_exit(PCIDevice *d)
pci_bridge_exitfn(d);
}
static Property rp_props[] = {
static const Property rp_props[] = {
DEFINE_PROP_BIT(COMPAT_PROP_PCP, PCIDevice, cap_present,
QEMU_PCIE_SLTCAP_PCP_BITNR, true),
DEFINE_PROP_BOOL("disable-acs", PCIESlot, disable_acs, false),

2
hw/pci-bridge/xio3130_downstream.c
View file

@ -134,7 +134,7 @@ static void xio3130_downstream_exitfn(PCIDevice *d)
pci_bridge_exitfn(d);
}
static Property xio3130_downstream_props[] = {
static const Property xio3130_downstream_props[] = {
DEFINE_PROP_BIT(COMPAT_PROP_PCP, PCIDevice, cap_present,
QEMU_PCIE_SLTCAP_PCP_BITNR, true),
DEFINE_PROP_END_OF_LIST()