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target/riscv: add support for Zcmp extension

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Add encode, trans* functions for Zcmp instructions.

Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230307081403.61950-7-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Weiwei Li 2023-03-07 16:13:59 +08:00 • committed by Alistair Francis
parent e0a3054f18
commit 193eb522e4
3 changed files with 209 additions and 1 deletions
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18
target/riscv/insn16.decode
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@ -21,6 +21,8 @@
%rs1_3 7:3 !function=ex_rvc_register
%rs2_3 2:3 !function=ex_rvc_register
%rs2_5 2:5
%r1s 7:3 !function=ex_sreg_register
%r2s 2:3 !function=ex_sreg_register
# Immediates:
%imm_ci 12:s1 2:5
@ -45,6 +47,8 @@
%uimm_cl_b 5:1 6:1
%uimm_cl_h 5:1 !function=ex_shift_1
%spimm 2:2 !function=ex_shift_4
%urlist 4:4
# Argument sets imported from insn32.decode:
&empty !extern
@ -56,7 +60,9 @@
&u imm rd !extern
&shift shamt rs1 rd !extern
&r2 rd rs1 !extern
&r2_s rs1 rs2 !extern
&cmpp urlist spimm
# Formats 16:
@cr .... ..... ..... .. &r rs2=%rs2_5 rs1=%rd %rd
@ -97,6 +103,8 @@
@cl_h ... . .. ... .. ... .. &i imm=%uimm_cl_h rs1=%rs1_3 rd=%rs2_3
@cs_b ... . .. ... .. ... .. &s imm=%uimm_cl_b rs1=%rs1_3 rs2=%rs2_3
@cs_h ... . .. ... .. ... .. &s imm=%uimm_cl_h rs1=%rs1_3 rs2=%rs2_3
@cm_pp ... ... ........ .. &cmpp %urlist %spimm
@cm_mv ... ... ... .. ... .. &r2_s rs2=%r2s rs1=%r1s
# *** RV32/64C Standard Extension (Quadrant 0) ***
{
@ -176,6 +184,16 @@ slli 000 . ..... ..... 10 @c_shift2
{
sq 101 ... ... .. ... 10 @c_sqsp
c_fsd 101 ...... ..... 10 @c_sdsp
# *** RV64 and RV32 Zcmp Extension ***
[
cm_push 101 11000 .... .. 10 @cm_pp
cm_pop 101 11010 .... .. 10 @cm_pp
cm_popret 101 11110 .... .. 10 @cm_pp
cm_popretz 101 11100 .... .. 10 @cm_pp
cm_mva01s 101 011 ... 11 ... 10 @cm_mv
cm_mvsa01 101 011 ... 01 ... 10 @cm_mv
]
}
sw 110 . ..... ..... 10 @c_swsp