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target/riscv: Add DisasExtend to gen_arith*

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Most arithmetic does not require extending the inputs.
Exceptions include division, comparison and minmax.

Begin using ctx->w, which allows elimination of gen_addw,
gen_subw, gen_mulw.

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210823195529.560295-7-richard.henderson@linaro.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Richard Henderson 2021-08-23 12:55:11 -07:00 • committed by Alistair Francis
parent ecda15d137
commit 191d1dafae
4 changed files with 64 additions and 90 deletions
Download patch file Download diff file Expand all files Collapse all files

39
target/riscv/insn_trans/trans_rvi.c.inc
View file

@ -230,7 +230,7 @@ static bool trans_sd(DisasContext *ctx, arg_sd *a)
static bool trans_addi(DisasContext *ctx, arg_addi *a)
{
return gen_arith_imm_fn(ctx, a, &tcg_gen_addi_tl);
return gen_arith_imm_fn(ctx, a, EXT_NONE, tcg_gen_addi_tl);
}
static void gen_slt(TCGv ret, TCGv s1, TCGv s2)
@ -243,29 +243,31 @@ static void gen_sltu(TCGv ret, TCGv s1, TCGv s2)
tcg_gen_setcond_tl(TCG_COND_LTU, ret, s1, s2);
}
static bool trans_slti(DisasContext *ctx, arg_slti *a)
{
return gen_arith_imm_tl(ctx, a, &gen_slt);
return gen_arith_imm_tl(ctx, a, EXT_SIGN, gen_slt);
}
static bool trans_sltiu(DisasContext *ctx, arg_sltiu *a)
{
return gen_arith_imm_tl(ctx, a, &gen_sltu);
return gen_arith_imm_tl(ctx, a, EXT_SIGN, gen_sltu);
}
static bool trans_xori(DisasContext *ctx, arg_xori *a)
{
return gen_arith_imm_fn(ctx, a, &tcg_gen_xori_tl);
return gen_arith_imm_fn(ctx, a, EXT_NONE, tcg_gen_xori_tl);
}
static bool trans_ori(DisasContext *ctx, arg_ori *a)
{
return gen_arith_imm_fn(ctx, a, &tcg_gen_ori_tl);
return gen_arith_imm_fn(ctx, a, EXT_NONE, tcg_gen_ori_tl);
}
static bool trans_andi(DisasContext *ctx, arg_andi *a)
{
return gen_arith_imm_fn(ctx, a, &tcg_gen_andi_tl);
return gen_arith_imm_fn(ctx, a, EXT_NONE, tcg_gen_andi_tl);
}
static bool trans_slli(DisasContext *ctx, arg_slli *a)
{
return gen_shifti(ctx, a, tcg_gen_shl_tl);
@ -283,12 +285,12 @@ static bool trans_srai(DisasContext *ctx, arg_srai *a)
static bool trans_add(DisasContext *ctx, arg_add *a)
{
return gen_arith(ctx, a, &tcg_gen_add_tl);
return gen_arith(ctx, a, EXT_NONE, tcg_gen_add_tl);
}
static bool trans_sub(DisasContext *ctx, arg_sub *a)
{
return gen_arith(ctx, a, &tcg_gen_sub_tl);
return gen_arith(ctx, a, EXT_NONE, tcg_gen_sub_tl);
}
static bool trans_sll(DisasContext *ctx, arg_sll *a)
@ -298,17 +300,17 @@ static bool trans_sll(DisasContext *ctx, arg_sll *a)
static bool trans_slt(DisasContext *ctx, arg_slt *a)
{
return gen_arith(ctx, a, &gen_slt);
return gen_arith(ctx, a, EXT_SIGN, gen_slt);
}
static bool trans_sltu(DisasContext *ctx, arg_sltu *a)
{
return gen_arith(ctx, a, &gen_sltu);
return gen_arith(ctx, a, EXT_SIGN, gen_sltu);
}
static bool trans_xor(DisasContext *ctx, arg_xor *a)
{
return gen_arith(ctx, a, &tcg_gen_xor_tl);
return gen_arith(ctx, a, EXT_NONE, tcg_gen_xor_tl);
}
static bool trans_srl(DisasContext *ctx, arg_srl *a)
@ -323,18 +325,19 @@ static bool trans_sra(DisasContext *ctx, arg_sra *a)
static bool trans_or(DisasContext *ctx, arg_or *a)
{
return gen_arith(ctx, a, &tcg_gen_or_tl);
return gen_arith(ctx, a, EXT_NONE, tcg_gen_or_tl);
}
static bool trans_and(DisasContext *ctx, arg_and *a)
{
return gen_arith(ctx, a, &tcg_gen_and_tl);
return gen_arith(ctx, a, EXT_NONE, tcg_gen_and_tl);
}
static bool trans_addiw(DisasContext *ctx, arg_addiw *a)
{
REQUIRE_64BIT(ctx);
return gen_arith_imm_tl(ctx, a, &gen_addw);
ctx->w = true;
return gen_arith_imm_fn(ctx, a, EXT_NONE, tcg_gen_addi_tl);
}
static bool trans_slliw(DisasContext *ctx, arg_slliw *a)
@ -370,13 +373,15 @@ static bool trans_sraiw(DisasContext *ctx, arg_sraiw *a)
static bool trans_addw(DisasContext *ctx, arg_addw *a)
{
REQUIRE_64BIT(ctx);
return gen_arith(ctx, a, &gen_addw);
ctx->w = true;
return gen_arith(ctx, a, EXT_NONE, tcg_gen_add_tl);
}
static bool trans_subw(DisasContext *ctx, arg_subw *a)
{
REQUIRE_64BIT(ctx);
return gen_arith(ctx, a, &gen_subw);
ctx->w = true;
return gen_arith(ctx, a, EXT_NONE, tcg_gen_sub_tl);
}
static bool trans_sllw(DisasContext *ctx, arg_sllw *a)