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lm32: translation routines
This patch adds the main translation routine. All opcodes of the LatticeMico32 processor are supported and translated to TCG ops. Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
This commit is contained in:
Michael Walle
Edgar E. Iglesias
parent
81ea0e1304
commit
17c0fa3d57
3 changed files with 1654 additions and 0 deletions
259
target-lm32/helper.c
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259
target-lm32/helper.c
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/*
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* LatticeMico32 helper routines.
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*
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* Copyright (c) 2010 Michael Walle <michael@walle.cc>
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include <stdio.h>
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#include <string.h>
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#include <assert.h>
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#include "config.h"
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#include "cpu.h"
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#include "exec-all.h"
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#include "host-utils.h"
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int cpu_lm32_handle_mmu_fault(CPUState *env, target_ulong address, int rw,
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int mmu_idx, int is_softmmu)
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{
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int prot;
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address &= TARGET_PAGE_MASK;
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prot = PAGE_BITS;
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if (env->flags & LM32_FLAG_IGNORE_MSB) {
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tlb_set_page(env, address, address & 0x7fffffff, prot, mmu_idx,
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TARGET_PAGE_SIZE);
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} else {
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tlb_set_page(env, address, address, prot, mmu_idx, TARGET_PAGE_SIZE);
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}
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return 0;
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}
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target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
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{
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return addr & TARGET_PAGE_MASK;
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}
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void do_interrupt(CPUState *env)
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{
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qemu_log_mask(CPU_LOG_INT,
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"exception at pc=%x type=%x\n", env->pc, env->exception_index);
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switch (env->exception_index) {
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case EXCP_INSN_BUS_ERROR:
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case EXCP_DATA_BUS_ERROR:
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case EXCP_DIVIDE_BY_ZERO:
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case EXCP_IRQ:
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case EXCP_SYSTEMCALL:
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/* non-debug exceptions */
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env->regs[R_EA] = env->pc;
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env->ie |= (env->ie & IE_IE) ? IE_EIE : 0;
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env->ie &= ~IE_IE;
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if (env->dc & DC_RE) {
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env->pc = env->deba + (env->exception_index * 32);
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} else {
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env->pc = env->eba + (env->exception_index * 32);
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}
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log_cpu_state_mask(CPU_LOG_INT, env, 0);
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break;
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case EXCP_BREAKPOINT:
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case EXCP_WATCHPOINT:
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/* debug exceptions */
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env->regs[R_BA] = env->pc;
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env->ie |= (env->ie & IE_IE) ? IE_BIE : 0;
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env->ie &= ~IE_IE;
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if (env->dc & DC_RE) {
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env->pc = env->deba + (env->exception_index * 32);
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} else {
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env->pc = env->eba + (env->exception_index * 32);
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}
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log_cpu_state_mask(CPU_LOG_INT, env, 0);
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break;
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default:
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cpu_abort(env, "unhandled exception type=%d\n",
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env->exception_index);
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break;
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}
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}
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typedef struct {
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const char *name;
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uint32_t revision;
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uint8_t num_interrupts;
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uint8_t num_breakpoints;
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uint8_t num_watchpoints;
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uint32_t features;
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} LM32Def;
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static const LM32Def lm32_defs[] = {
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{
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.name = "lm32-basic",
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.revision = 3,
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.num_interrupts = 32,
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.num_breakpoints = 4,
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.num_watchpoints = 4,
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.features = (LM32_FEATURE_SHIFT
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| LM32_FEATURE_SIGN_EXTEND
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| LM32_FEATURE_CYCLE_COUNT),
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},
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{
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.name = "lm32-standard",
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.revision = 3,
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.num_interrupts = 32,
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.num_breakpoints = 4,
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.num_watchpoints = 4,
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.features = (LM32_FEATURE_MULTIPLY
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| LM32_FEATURE_DIVIDE
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| LM32_FEATURE_SHIFT
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| LM32_FEATURE_SIGN_EXTEND
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| LM32_FEATURE_I_CACHE
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| LM32_FEATURE_CYCLE_COUNT),
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},
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{
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.name = "lm32-full",
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.revision = 3,
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.num_interrupts = 32,
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.num_breakpoints = 4,
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.num_watchpoints = 4,
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.features = (LM32_FEATURE_MULTIPLY
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| LM32_FEATURE_DIVIDE
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| LM32_FEATURE_SHIFT
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| LM32_FEATURE_SIGN_EXTEND
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| LM32_FEATURE_I_CACHE
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| LM32_FEATURE_D_CACHE
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| LM32_FEATURE_CYCLE_COUNT),
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}
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};
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void cpu_lm32_list(FILE *f, fprintf_function cpu_fprintf)
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{
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int i;
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cpu_fprintf(f, "Available CPUs:\n");
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for (i = 0; i < ARRAY_SIZE(lm32_defs); i++) {
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cpu_fprintf(f, " %s\n", lm32_defs[i].name);
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}
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}
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static const LM32Def *cpu_lm32_find_by_name(const char *name)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(lm32_defs); i++) {
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if (strcasecmp(name, lm32_defs[i].name) == 0) {
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return &lm32_defs[i];
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}
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}
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return NULL;
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}
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static uint32_t cfg_by_def(const LM32Def *def)
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{
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uint32_t cfg = 0;
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if (def->features & LM32_FEATURE_MULTIPLY) {
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cfg |= CFG_M;
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}
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if (def->features & LM32_FEATURE_DIVIDE) {
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cfg |= CFG_D;
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}
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if (def->features & LM32_FEATURE_SHIFT) {
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cfg |= CFG_S;
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}
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if (def->features & LM32_FEATURE_SIGN_EXTEND) {
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cfg |= CFG_X;
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}
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if (def->features & LM32_FEATURE_I_CACHE) {
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cfg |= CFG_IC;
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}
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if (def->features & LM32_FEATURE_D_CACHE) {
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cfg |= CFG_DC;
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}
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if (def->features & LM32_FEATURE_CYCLE_COUNT) {
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cfg |= CFG_CC;
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}
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cfg |= (def->num_interrupts << CFG_INT_SHIFT);
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cfg |= (def->num_breakpoints << CFG_BP_SHIFT);
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cfg |= (def->num_watchpoints << CFG_WP_SHIFT);
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cfg |= (def->revision << CFG_REV_SHIFT);
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return cfg;
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}
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CPUState *cpu_lm32_init(const char *cpu_model)
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{
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CPUState *env;
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const LM32Def *def;
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static int tcg_initialized;
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def = cpu_lm32_find_by_name(cpu_model);
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if (!def) {
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return NULL;
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}
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env = qemu_mallocz(sizeof(CPUState));
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env->features = def->features;
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env->num_bps = def->num_breakpoints;
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env->num_wps = def->num_watchpoints;
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env->cfg = cfg_by_def(def);
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env->flags = 0;
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cpu_exec_init(env);
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cpu_reset(env);
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if (!tcg_initialized) {
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tcg_initialized = 1;
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lm32_translate_init();
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}
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return env;
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}
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/* Some soc ignores the MSB on the address bus. Thus creating a shadow memory
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* area. As a general rule, 0x00000000-0x7fffffff is cached, whereas
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* 0x80000000-0xffffffff is not cached and used to access IO devices. */
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void cpu_lm32_set_phys_msb_ignore(CPUState *env, int value)
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{
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if (value) {
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env->flags |= LM32_FLAG_IGNORE_MSB;
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} else {
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env->flags &= ~LM32_FLAG_IGNORE_MSB;
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}
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}
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void cpu_reset(CPUState *env)
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{
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if (qemu_loglevel_mask(CPU_LOG_RESET)) {
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qemu_log("CPU Reset (CPU %d)\n", env->cpu_index);
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log_cpu_state(env, 0);
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}
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tlb_flush(env, 1);
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/* reset cpu state */
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memset(env, 0, offsetof(CPULM32State, breakpoints));
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}
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