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target/sparc: fake UltraSPARC T1 PCR and PIC registers

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Fake access to
   PCR Performance Control Register
and
   PIC Performance Instrumentation Counter.

Ignore writes in privileged mode, and return 0 on reads.

This allows booting Tribblix, MilaX and v9os under Niagara target.

Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20250209211248.50383-1-atar4qemu@gmail.com>
This commit is contained in:
Artyom Tarasenko 2025-02-09 22:12:48 +01:00 • committed by Richard Henderson
parent 7a74e46808
commit 172e7644f3
2 changed files with 25 additions and 1 deletions
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7
target/sparc/insns.decode
View file

@ -96,7 +96,10 @@ CALL 01 i:s30
RDTICK 10 rd:5 101000 00100 0 0000000000000 RDTICK 10 rd:5 101000 00100 0 0000000000000
RDPC 10 rd:5 101000 00101 0 0000000000000 RDPC 10 rd:5 101000 00101 0 0000000000000
RDFPRS 10 rd:5 101000 00110 0 0000000000000 RDFPRS 10 rd:5 101000 00110 0 0000000000000
RDASR17 10 rd:5 101000 10001 0 0000000000000 {
RDASR17 10 rd:5 101000 10001 0 0000000000000
RDPIC 10 rd:5 101000 10001 0 0000000000000
}
RDGSR 10 rd:5 101000 10011 0 0000000000000 RDGSR 10 rd:5 101000 10011 0 0000000000000
RDSOFTINT 10 rd:5 101000 10110 0 0000000000000 RDSOFTINT 10 rd:5 101000 10110 0 0000000000000
RDTICK_CMPR 10 rd:5 101000 10111 0 0000000000000 RDTICK_CMPR 10 rd:5 101000 10111 0 0000000000000
@ -114,6 +117,8 @@ CALL 01 i:s30
WRCCR 10 00010 110000 ..... . ............. @n_r_ri WRCCR 10 00010 110000 ..... . ............. @n_r_ri
WRASI 10 00011 110000 ..... . ............. @n_r_ri WRASI 10 00011 110000 ..... . ............. @n_r_ri
WRFPRS 10 00110 110000 ..... . ............. @n_r_ri WRFPRS 10 00110 110000 ..... . ............. @n_r_ri
WRPCR 10 10000 110000 01000 0 0000000000000
WRPIC 10 10001 110000 01000 0 0000000000000
{ {
WRGSR 10 10011 110000 ..... . ............. @n_r_ri WRGSR 10 10011 110000 ..... . ............. @n_r_ri
WRPOWERDOWN 10 10011 110000 ..... . ............. @n_r_ri WRPOWERDOWN 10 10011 110000 ..... . ............. @n_r_ri

19
target/sparc/translate.c
View file

@ -2882,6 +2882,14 @@ static TCGv do_rd_leon3_config(DisasContext *dc, TCGv dst)
TRANS(RDASR17, ASR17, do_rd_special, true, a->rd, do_rd_leon3_config) TRANS(RDASR17, ASR17, do_rd_special, true, a->rd, do_rd_leon3_config)
static TCGv do_rdpic(DisasContext *dc, TCGv dst)
{
return tcg_constant_tl(0);
}
TRANS(RDPIC, HYPV, do_rd_special, supervisor(dc), a->rd, do_rdpic)
static TCGv do_rdccr(DisasContext *dc, TCGv dst) static TCGv do_rdccr(DisasContext *dc, TCGv dst)
{ {
gen_helper_rdccr(dst, tcg_env); gen_helper_rdccr(dst, tcg_env);
@ -3315,6 +3323,17 @@ static void do_wrfprs(DisasContext *dc, TCGv src)
TRANS(WRFPRS, 64, do_wr_special, a, true, do_wrfprs) TRANS(WRFPRS, 64, do_wr_special, a, true, do_wrfprs)
static bool do_priv_nop(DisasContext *dc, bool priv)
{
if (!priv) {
return raise_priv(dc);
}
return advance_pc(dc);
}
TRANS(WRPCR, HYPV, do_priv_nop, supervisor(dc))
TRANS(WRPIC, HYPV, do_priv_nop, supervisor(dc))
static void do_wrgsr(DisasContext *dc, TCGv src) static void do_wrgsr(DisasContext *dc, TCGv src)
{ {
gen_trap_ifnofpu(dc); gen_trap_ifnofpu(dc);