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target/mips: Add fields for SAARI and SAAR CP0 registers
Add fields for SAARI and SAAR CP0 registers. Reviewed-by: Stefan Markovic <smarkovic@wavecomp.com> Signed-off-by: Yongbok Kim <yongbok.kim@mips.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
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2 changed files with 12 additions and 4 deletions
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@ -214,8 +214,8 @@ const VMStateDescription vmstate_tlb = {
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const VMStateDescription vmstate_mips_cpu = {
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.name = "cpu",
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.version_id = 15,
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.minimum_version_id = 15,
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.version_id = 16,
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.minimum_version_id = 16,
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.post_load = cpu_post_load,
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.fields = (VMStateField[]) {
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/* Active TC */
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@ -274,6 +274,8 @@ const VMStateDescription vmstate_mips_cpu = {
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VMSTATE_UINT32(env.CP0_BadInstrP, MIPSCPU),
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VMSTATE_UINT32(env.CP0_BadInstrX, MIPSCPU),
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VMSTATE_INT32(env.CP0_Count, MIPSCPU),
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VMSTATE_UINT32(env.CP0_SAARI, MIPSCPU),
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VMSTATE_UINT64_ARRAY(env.CP0_SAAR, MIPSCPU, 2),
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VMSTATE_UINTTL(env.CP0_EntryHi, MIPSCPU),
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VMSTATE_INT32(env.CP0_Compare, MIPSCPU),
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VMSTATE_INT32(env.CP0_Status, MIPSCPU),
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