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target/arm: Create and use new function arm_v7m_is_handler_mode()
Add a utility function for testing whether the CPU is in Handler mode; this is just a check whether v7m.exception is non-zero, but we do it in several places and it makes the code a bit easier to read to not have to mentally figure out what the test is testing. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 1501692241-23310-14-git-send-email-peter.maydell@linaro.org
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2 changed files with 12 additions and 6 deletions
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@ -6142,7 +6142,7 @@ static void do_v7m_exception_exit(ARMCPU *cpu)
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* that jumps to magic addresses don't have magic behaviour unless
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* we're in Handler mode (compare pseudocode BXWritePC()).
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*/
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assert(env->v7m.exception != 0);
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assert(arm_v7m_is_handler_mode(env));
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/* In the spec pseudocode ExceptionReturn() is called directly
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* from BXWritePC() and gets the full target PC value including
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@ -6249,7 +6249,7 @@ static void do_v7m_exception_exit(ARMCPU *cpu)
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* resuming in Thread mode. If that doesn't match what the
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* exception return type specified then this is a UsageFault.
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*/
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if (return_to_handler == (env->v7m.exception == 0)) {
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if (return_to_handler != arm_v7m_is_handler_mode(env)) {
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/* Take an INVPC UsageFault by pushing the stack again. */
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armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE);
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env->v7m.cfsr |= R_V7M_CFSR_INVPC_MASK;
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@ -6400,7 +6400,7 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs)
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if (env->v7m.control & R_V7M_CONTROL_SPSEL_MASK) {
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lr |= 4;
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}
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if (env->v7m.exception == 0) {
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if (!arm_v7m_is_handler_mode(env)) {
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lr |= 8;
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}
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@ -8793,7 +8793,7 @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskreg, uint32_t val)
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* switch_v7m_sp() deals with updating the SPSEL bit in
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* env->v7m.control, so we only need update the others.
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*/
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if (env->v7m.exception == 0) {
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if (!arm_v7m_is_handler_mode(env)) {
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switch_v7m_sp(env, (val & R_V7M_CONTROL_SPSEL_MASK) != 0);
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}
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env->v7m.control &= ~R_V7M_CONTROL_NPRIV_MASK;
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