mirror of
https://github.com/Motorhead1991/qemu.git
synced 2025-08-03 15:53:54 -06:00
target-arm queue:
* Handle atomic updates of page tables entries in MMIO during PTW * Advertise Cortex-A53 erratum #843419 fix via REVIDR * MAINTAINERS: Cover hw/ide/ahci-allwinner.c with AllWinner A10 machine * misc: m48t59: replace qemu_system_reset_request() call with watchdog_perform_action() * misc: pxa2xx_timer: replace qemu_system_reset_request() call with watchdog_perform_action() * xlnx-versal-ospi: disable reentrancy detection for iomem_dac * sbsa-ref: Simplify init since PCIe is always enabled * stm32l4x5: Use TYPE_OR_IRQ when connecting STM32L4x5 EXTI fan-in IRQs * pl031: Update last RTCLR value on write in case it's read back * block: m25p80: Add support of mt35xu02gbba * xlnx-versal-virt: Add machine property ospi-flash * reset: refactor system reset to be three-phase aware * new board model raspi4b -----BEGIN PGP SIGNATURE----- iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAmXeAMEZHHBldGVyLm1h eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3syyD/4lJzzstbDIAsu94Z4Hi0So CFLAMJFsPy3fMsU2IqVP+TDTyhUeMPebwfj7sQHUtQcXVh5i1/HlYgdUgXsnjGWQ pc6BxycpW6uJWYb7Ma3CdSGS+hxEpQ+U8Qeijwqg0kAqhjNtrSIkTRQ4u8p8T+kN dWtQzp7D15BpEVhWl/2dLWWJwV3H6TThmr1FbK5wl/c7hJzy2uaXqmmCvercU0Zo 6ab3SnGyhaujdd/FsDvhnVEYqcmcO2p9UtSnGAbdfw0zsf4p8cS2Q6M9q4DHBFYn 6Bt51DFP5D+114VpqRSXF2Lv9K8swjTgqhDld9vCoios6pS3LMwcTAcONUxE8JU+ uD7kXTN/lv3atNEy4MTFkTeNtKgbYJJuPwWrDRNdbVXPwrEHGWN3+ZYISmuYb+p+ XL2/7HeP7/qEVMW2d18+7OCriZwKiBRZRKUrtG7mQSBZEMetbhpA+mLcxAZT0FAl 18O/mcvEJrrE7x6Bqyv96b8PE0/er5cVg/b/wrkKS8DL4NWU9bJSjJNRrvt9bvvl jSzPGo4ngHlfO0OpurLoFOZCVxKWVXgaKkQ3pOz301nsDyhEndNLeCxrITac8G2Q C/WQuMaeOoV1x7N2MzaCQmyRzy8yGkG9av0aI/8feobfV/Yg4wPsfhcEn/XQWXKv NUJ4/z78FbJlI2JeDP2QSA== =xaMv -----END PGP SIGNATURE----- Merge tag 'pull-target-arm-20240227-1' of https://git.linaro.org/people/pmaydell/qemu-arm into staging target-arm queue: * Handle atomic updates of page tables entries in MMIO during PTW * Advertise Cortex-A53 erratum #843419 fix via REVIDR * MAINTAINERS: Cover hw/ide/ahci-allwinner.c with AllWinner A10 machine * misc: m48t59: replace qemu_system_reset_request() call with watchdog_perform_action() * misc: pxa2xx_timer: replace qemu_system_reset_request() call with watchdog_perform_action() * xlnx-versal-ospi: disable reentrancy detection for iomem_dac * sbsa-ref: Simplify init since PCIe is always enabled * stm32l4x5: Use TYPE_OR_IRQ when connecting STM32L4x5 EXTI fan-in IRQs * pl031: Update last RTCLR value on write in case it's read back * block: m25p80: Add support of mt35xu02gbba * xlnx-versal-virt: Add machine property ospi-flash * reset: refactor system reset to be three-phase aware * new board model raspi4b # -----BEGIN PGP SIGNATURE----- # # iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAmXeAMEZHHBldGVyLm1h # eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3syyD/4lJzzstbDIAsu94Z4Hi0So # CFLAMJFsPy3fMsU2IqVP+TDTyhUeMPebwfj7sQHUtQcXVh5i1/HlYgdUgXsnjGWQ # pc6BxycpW6uJWYb7Ma3CdSGS+hxEpQ+U8Qeijwqg0kAqhjNtrSIkTRQ4u8p8T+kN # dWtQzp7D15BpEVhWl/2dLWWJwV3H6TThmr1FbK5wl/c7hJzy2uaXqmmCvercU0Zo # 6ab3SnGyhaujdd/FsDvhnVEYqcmcO2p9UtSnGAbdfw0zsf4p8cS2Q6M9q4DHBFYn # 6Bt51DFP5D+114VpqRSXF2Lv9K8swjTgqhDld9vCoios6pS3LMwcTAcONUxE8JU+ # uD7kXTN/lv3atNEy4MTFkTeNtKgbYJJuPwWrDRNdbVXPwrEHGWN3+ZYISmuYb+p+ # XL2/7HeP7/qEVMW2d18+7OCriZwKiBRZRKUrtG7mQSBZEMetbhpA+mLcxAZT0FAl # 18O/mcvEJrrE7x6Bqyv96b8PE0/er5cVg/b/wrkKS8DL4NWU9bJSjJNRrvt9bvvl # jSzPGo4ngHlfO0OpurLoFOZCVxKWVXgaKkQ3pOz301nsDyhEndNLeCxrITac8G2Q # C/WQuMaeOoV1x7N2MzaCQmyRzy8yGkG9av0aI/8feobfV/Yg4wPsfhcEn/XQWXKv # NUJ4/z78FbJlI2JeDP2QSA== # =xaMv # -----END PGP SIGNATURE----- # gpg: Signature made Tue 27 Feb 2024 15:33:21 GMT # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate] # gpg: aka "Peter Maydell <peter@archaic.org.uk>" [ultimate] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * tag 'pull-target-arm-20240227-1' of https://git.linaro.org/people/pmaydell/qemu-arm: (36 commits) docs/system/arm: Add RPi4B to raspi.rst hw/misc/bcm2835_property: Add missed BCM2835 properties tests/avocado/boot_linux_console.py: Add Rpi4b boot tests hw/arm/bcm2838_peripherals: Add clock_isp stub hw/arm: Add memory region for BCM2837 RPiVid ASB hw/arm/raspi4b: Temporarily disable unimplemented rpi4b devices hw/arm: Introduce Raspberry PI 4 machine hw/arm: Add GPIO and SD to BCM2838 periph hw/gpio: Connect SD controller to BCM2838 GPIO hw/gpio: Implement BCM2838 GPIO functionality hw/gpio: Add BCM2838 GPIO stub hw/arm/bcm2838: Add GIC-400 to BCM2838 SoC hw/arm: Introduce BCM2838 SoC hw/arm/raspi: Split out raspi machine common part hw/arm/bcm2853_peripherals: Split out common part of peripherals hw/arm/bcm2836: Split out common part of BCM283X classes docs/devel/reset: Update to discuss system reset hw/core/machine: Use qemu_register_resettable for sysbus reset hw/core/reset: Implement qemu_register_reset via qemu_register_resettable hw/core/reset: Add qemu_{register, unregister}_resettable() ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell
commit
158a054c4d
46 changed files with 2503 additions and 305 deletions
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@ -35,10 +35,13 @@
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#include "hw/misc/unimp.h"
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#include "qom/object.h"
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#define TYPE_BCM_SOC_PERIPHERALS_BASE "bcm-soc-peripherals-base"
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OBJECT_DECLARE_TYPE(BCMSocPeripheralBaseState, BCMSocPeripheralBaseClass,
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BCM_SOC_PERIPHERALS_BASE)
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#define TYPE_BCM2835_PERIPHERALS "bcm2835-peripherals"
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OBJECT_DECLARE_SIMPLE_TYPE(BCM2835PeripheralState, BCM2835_PERIPHERALS)
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struct BCM2835PeripheralState {
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struct BCMSocPeripheralBaseState {
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/*< private >*/
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SysBusDevice parent_obj;
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/*< public >*/
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@ -60,12 +63,9 @@ struct BCM2835PeripheralState {
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OrIRQState orgated_dma_irq;
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BCM2835ICState ic;
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BCM2835PropertyState property;
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BCM2835RngState rng;
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BCM2835MboxState mboxes;
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SDHCIState sdhci;
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BCM2835SDHostState sdhost;
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BCM2835GpioState gpio;
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Bcm2835ThermalState thermal;
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UnimplementedDeviceState i2s;
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BCM2835SPIState spi[1];
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UnimplementedDeviceState i2c[3];
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@ -79,4 +79,25 @@ struct BCM2835PeripheralState {
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UnimplementedDeviceState sdramc;
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};
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struct BCMSocPeripheralBaseClass {
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/*< private >*/
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SysBusDeviceClass parent_class;
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/*< public >*/
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uint64_t peri_size; /* Peripheral range size */
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};
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struct BCM2835PeripheralState {
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/*< private >*/
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BCMSocPeripheralBaseState parent_obj;
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/*< public >*/
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BCM2835RngState rng;
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Bcm2835ThermalState thermal;
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BCM2835GpioState gpio;
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};
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void create_unimp(BCMSocPeripheralBaseState *ps,
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UnimplementedDeviceState *uds,
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const char *name, hwaddr ofs, hwaddr size);
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void bcm_soc_peripherals_common_realize(DeviceState *dev, Error **errp);
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#endif /* BCM2835_PERIPHERALS_H */
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@ -17,8 +17,10 @@
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#include "target/arm/cpu.h"
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#include "qom/object.h"
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#define TYPE_BCM283X_BASE "bcm283x-base"
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OBJECT_DECLARE_TYPE(BCM283XBaseState, BCM283XBaseClass, BCM283X_BASE)
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#define TYPE_BCM283X "bcm283x"
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OBJECT_DECLARE_TYPE(BCM283XState, BCM283XClass, BCM283X)
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OBJECT_DECLARE_SIMPLE_TYPE(BCM283XState, BCM283X)
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#define BCM283X_NCPUS 4
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@ -30,7 +32,7 @@ OBJECT_DECLARE_TYPE(BCM283XState, BCM283XClass, BCM283X)
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#define TYPE_BCM2836 "bcm2836"
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#define TYPE_BCM2837 "bcm2837"
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struct BCM283XState {
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struct BCM283XBaseState {
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/*< private >*/
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DeviceState parent_obj;
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/*< public >*/
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@ -41,7 +43,28 @@ struct BCM283XState {
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ARMCPU core;
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} cpu[BCM283X_NCPUS];
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BCM2836ControlState control;
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};
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struct BCM283XBaseClass {
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/*< private >*/
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DeviceClass parent_class;
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/*< public >*/
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const char *name;
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const char *cpu_type;
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unsigned core_count;
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hwaddr peri_base; /* Peripheral base address seen by the CPU */
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hwaddr ctrl_base; /* Interrupt controller and mailboxes etc. */
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int clusterid;
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};
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struct BCM283XState {
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/*< private >*/
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BCM283XBaseState parent_obj;
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/*< public >*/
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BCM2835PeripheralState peripherals;
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};
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bool bcm283x_common_realize(DeviceState *dev, BCMSocPeripheralBaseState *ps,
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Error **errp);
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#endif /* BCM2836_H */
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31
include/hw/arm/bcm2838.h
Normal file
31
include/hw/arm/bcm2838.h
Normal file
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@ -0,0 +1,31 @@
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/*
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* BCM2838 SoC emulation
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*
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* Copyright (C) 2022 Ovchinnikov Vitalii <vitalii.ovchinnikov@auriga.com>
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*
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* SPDX-License-Identifier: GPL-2.0-or-later
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*/
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#ifndef BCM2838_H
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#define BCM2838_H
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#include "hw/arm/bcm2836.h"
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#include "hw/intc/arm_gic.h"
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#include "hw/arm/bcm2838_peripherals.h"
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#define BCM2838_PERI_LOW_BASE 0xfc000000
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#define BCM2838_GIC_BASE 0x40000
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#define TYPE_BCM2838 "bcm2838"
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OBJECT_DECLARE_TYPE(BCM2838State, BCM2838Class, BCM2838)
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struct BCM2838State {
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/*< private >*/
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BCM283XBaseState parent_obj;
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/*< public >*/
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BCM2838PeripheralState peripherals;
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GICState gic;
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};
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#endif /* BCM2838_H */
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84
include/hw/arm/bcm2838_peripherals.h
Normal file
84
include/hw/arm/bcm2838_peripherals.h
Normal file
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@ -0,0 +1,84 @@
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/*
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* BCM2838 peripherals emulation
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*
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* Copyright (C) 2022 Ovchinnikov Vitalii <vitalii.ovchinnikov@auriga.com>
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*
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* SPDX-License-Identifier: GPL-2.0-or-later
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*/
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#ifndef BCM2838_PERIPHERALS_H
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#define BCM2838_PERIPHERALS_H
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#include "hw/arm/bcm2835_peripherals.h"
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#include "hw/sd/sdhci.h"
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#include "hw/gpio/bcm2838_gpio.h"
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/* SPI */
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#define GIC_SPI_INTERRUPT_MBOX 33
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#define GIC_SPI_INTERRUPT_MPHI 40
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#define GIC_SPI_INTERRUPT_DWC2 73
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#define GIC_SPI_INTERRUPT_DMA_0 80
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#define GIC_SPI_INTERRUPT_DMA_6 86
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#define GIC_SPI_INTERRUPT_DMA_7_8 87
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#define GIC_SPI_INTERRUPT_DMA_9_10 88
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#define GIC_SPI_INTERRUPT_AUX_UART1 93
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#define GIC_SPI_INTERRUPT_SDHOST 120
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#define GIC_SPI_INTERRUPT_UART0 121
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#define GIC_SPI_INTERRUPT_RNG200 125
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#define GIC_SPI_INTERRUPT_EMMC_EMMC2 126
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#define GIC_SPI_INTERRUPT_PCI_INT_A 143
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#define GIC_SPI_INTERRUPT_GENET_A 157
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#define GIC_SPI_INTERRUPT_GENET_B 158
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/* GPU (legacy) DMA interrupts */
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#define GPU_INTERRUPT_DMA0 16
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#define GPU_INTERRUPT_DMA1 17
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#define GPU_INTERRUPT_DMA2 18
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#define GPU_INTERRUPT_DMA3 19
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#define GPU_INTERRUPT_DMA4 20
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#define GPU_INTERRUPT_DMA5 21
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#define GPU_INTERRUPT_DMA6 22
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#define GPU_INTERRUPT_DMA7_8 23
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#define GPU_INTERRUPT_DMA9_10 24
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#define GPU_INTERRUPT_DMA11 25
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#define GPU_INTERRUPT_DMA12 26
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#define GPU_INTERRUPT_DMA13 27
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#define GPU_INTERRUPT_DMA14 28
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#define GPU_INTERRUPT_DMA15 31
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#define BCM2838_MPHI_OFFSET 0xb200
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#define BCM2838_MPHI_SIZE 0x200
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#define TYPE_BCM2838_PERIPHERALS "bcm2838-peripherals"
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OBJECT_DECLARE_TYPE(BCM2838PeripheralState, BCM2838PeripheralClass,
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BCM2838_PERIPHERALS)
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struct BCM2838PeripheralState {
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/*< private >*/
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BCMSocPeripheralBaseState parent_obj;
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/*< public >*/
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MemoryRegion peri_low_mr;
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MemoryRegion peri_low_mr_alias;
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MemoryRegion mphi_mr_alias;
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SDHCIState emmc2;
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BCM2838GpioState gpio;
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OrIRQState mmc_irq_orgate;
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OrIRQState dma_7_8_irq_orgate;
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OrIRQState dma_9_10_irq_orgate;
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UnimplementedDeviceState asb;
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UnimplementedDeviceState clkisp;
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};
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struct BCM2838PeripheralClass {
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/*< private >*/
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BCMSocPeripheralBaseClass parent_class;
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/*< public >*/
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uint64_t peri_low_size; /* Peripheral lower range size */
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};
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#endif /* BCM2838_PERIPHERALS_H */
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@ -159,4 +159,15 @@ enum rpi_firmware_clk_id {
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RPI_FIRMWARE_NUM_CLK_ID,
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};
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struct rpi_firmware_property_tag_header {
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uint32_t tag;
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uint32_t buf_size;
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uint32_t req_resp_size;
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};
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typedef struct rpi_firmware_prop_request {
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struct rpi_firmware_property_tag_header hdr;
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uint8_t payload[0];
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} rpi_firmware_prop_request_t;
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#endif /* INCLUDE_HW_MISC_RASPBERRYPI_FW_DEFS_H_ */
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@ -28,6 +28,42 @@
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#ifndef HW_ARM_RASPI_PLATFORM_H
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#define HW_ARM_RASPI_PLATFORM_H
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#include "hw/boards.h"
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#include "hw/arm/boot.h"
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/* Registered machine type (matches RPi Foundation bootloader and U-Boot) */
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#define MACH_TYPE_BCM2708 3138
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#define TYPE_RASPI_BASE_MACHINE MACHINE_TYPE_NAME("raspi-base")
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OBJECT_DECLARE_TYPE(RaspiBaseMachineState, RaspiBaseMachineClass,
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RASPI_BASE_MACHINE)
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struct RaspiBaseMachineState {
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/*< private >*/
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MachineState parent_obj;
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/*< public >*/
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struct arm_boot_info binfo;
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};
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struct RaspiBaseMachineClass {
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/*< private >*/
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MachineClass parent_obj;
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/*< public >*/
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uint32_t board_rev;
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};
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/* Common functions for raspberry pi machines */
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const char *board_soc_type(uint32_t board_rev);
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void raspi_machine_init(MachineState *machine);
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typedef struct BCM283XBaseState BCM283XBaseState;
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void raspi_base_machine_init(MachineState *machine,
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BCM283XBaseState *soc);
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void raspi_machine_class_common_init(MachineClass *mc,
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uint32_t board_rev);
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uint64_t board_ram_size(uint32_t board_rev);
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#define MSYNC_OFFSET 0x0000 /* Multicore Sync Block */
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#define CCPT_OFFSET 0x1000 /* Compact Camera Port 2 TX */
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#define INTE_OFFSET 0x2000 /* VC Interrupt controller */
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@ -37,7 +73,7 @@
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#define MPHI_OFFSET 0x6000 /* Message-based Parallel Host Intf. */
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#define DMA_OFFSET 0x7000 /* DMA controller, channels 0-14 */
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#define ARBA_OFFSET 0x9000
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#define BRDG_OFFSET 0xa000
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#define BRDG_OFFSET 0xa000 /* RPiVid ASB for BCM2838 (BCM2711) */
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#define ARM_OFFSET 0xB000 /* ARM control block */
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#define ARMCTRL_OFFSET (ARM_OFFSET + 0x000)
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#define ARMCTRL_IC_OFFSET (ARM_OFFSET + 0x200) /* Interrupt controller */
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@ -26,6 +26,7 @@
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#include "exec/memory.h"
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#include "hw/arm/armv7m.h"
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#include "hw/or-irq.h"
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#include "hw/misc/stm32l4x5_syscfg.h"
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#include "hw/misc/stm32l4x5_exti.h"
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#include "qom/object.h"
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@ -36,12 +37,15 @@
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#define TYPE_STM32L4X5XG_SOC "stm32l4x5xg-soc"
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OBJECT_DECLARE_TYPE(Stm32l4x5SocState, Stm32l4x5SocClass, STM32L4X5_SOC)
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|
||||
#define NUM_EXTI_OR_GATES 4
|
||||
|
||||
struct Stm32l4x5SocState {
|
||||
SysBusDevice parent_obj;
|
||||
|
||||
ARMv7MState armv7m;
|
||||
|
||||
Stm32l4x5ExtiState exti;
|
||||
OrIRQState exti_or_gates[NUM_EXTI_OR_GATES];
|
||||
Stm32l4x5SyscfgState syscfg;
|
||||
|
||||
MemoryRegion sram1;
|
||||
|
|
|
|||
48
include/hw/core/resetcontainer.h
Normal file
48
include/hw/core/resetcontainer.h
Normal file
|
|
@ -0,0 +1,48 @@
|
|||
/*
|
||||
* Reset container
|
||||
*
|
||||
* Copyright (c) 2024 Linaro, Ltd
|
||||
*
|
||||
* This work is licensed under the terms of the GNU GPL, version 2 or later.
|
||||
* See the COPYING file in the top-level directory.
|
||||
*/
|
||||
|
||||
#ifndef HW_RESETCONTAINER_H
|
||||
#define HW_RESETCONTAINER_H
|
||||
|
||||
/*
|
||||
* The "reset container" is an object which implements the Resettable
|
||||
* interface. It contains a list of arbitrary other objects which also
|
||||
* implement Resettable. Resetting the reset container resets all the
|
||||
* objects in it.
|
||||
*/
|
||||
|
||||
#include "qom/object.h"
|
||||
|
||||
#define TYPE_RESETTABLE_CONTAINER "resettable-container"
|
||||
OBJECT_DECLARE_TYPE(ResettableContainer, ResettableContainerClass, RESETTABLE_CONTAINER)
|
||||
|
||||
/**
|
||||
* resettable_container_add: Add a resettable object to the container
|
||||
* @rc: container
|
||||
* @obj: object to add to the container
|
||||
*
|
||||
* Add @obj to the ResettableContainer @rc. @obj must implement the
|
||||
* Resettable interface.
|
||||
*
|
||||
* When @rc is reset, it will reset every object that has been added
|
||||
* to it, in the order they were added.
|
||||
*/
|
||||
void resettable_container_add(ResettableContainer *rc, Object *obj);
|
||||
|
||||
/**
|
||||
* resettable_container_remove: Remove an object from the container
|
||||
* @rc: container
|
||||
* @obj: object to remove from the container
|
||||
*
|
||||
* Remove @obj from the ResettableContainer @rc. @obj must have been
|
||||
* previously added to this container.
|
||||
*/
|
||||
void resettable_container_remove(ResettableContainer *rc, Object *obj);
|
||||
|
||||
#endif
|
||||
|
|
@ -16,6 +16,8 @@
|
|||
#include "ui/console.h"
|
||||
#include "qom/object.h"
|
||||
|
||||
#define UPPER_RAM_BASE 0x40000000
|
||||
|
||||
#define TYPE_BCM2835_FB "bcm2835-fb"
|
||||
OBJECT_DECLARE_SIMPLE_TYPE(BCM2835FBState, BCM2835_FB)
|
||||
|
||||
|
|
|
|||
45
include/hw/gpio/bcm2838_gpio.h
Normal file
45
include/hw/gpio/bcm2838_gpio.h
Normal file
|
|
@ -0,0 +1,45 @@
|
|||
/*
|
||||
* Raspberry Pi (BCM2838) GPIO Controller
|
||||
* This implementation is based on bcm2835_gpio (hw/gpio/bcm2835_gpio.c)
|
||||
*
|
||||
* Copyright (c) 2022 Auriga LLC
|
||||
*
|
||||
* Authors:
|
||||
* Lotosh, Aleksey <aleksey.lotosh@auriga.com>
|
||||
*
|
||||
* This work is licensed under the terms of the GNU GPL, version 2 or later.
|
||||
* See the COPYING file in the top-level directory.
|
||||
*/
|
||||
|
||||
#ifndef BCM2838_GPIO_H
|
||||
#define BCM2838_GPIO_H
|
||||
|
||||
#include "hw/sd/sd.h"
|
||||
#include "hw/sysbus.h"
|
||||
#include "qom/object.h"
|
||||
|
||||
#define TYPE_BCM2838_GPIO "bcm2838-gpio"
|
||||
OBJECT_DECLARE_SIMPLE_TYPE(BCM2838GpioState, BCM2838_GPIO)
|
||||
|
||||
#define BCM2838_GPIO_REGS_SIZE 0x1000
|
||||
#define BCM2838_GPIO_NUM 58
|
||||
#define GPIO_PUP_PDN_CNTRL_NUM 4
|
||||
|
||||
struct BCM2838GpioState {
|
||||
SysBusDevice parent_obj;
|
||||
|
||||
MemoryRegion iomem;
|
||||
|
||||
/* SDBus selector */
|
||||
SDBus sdbus;
|
||||
SDBus *sdbus_sdhci;
|
||||
SDBus *sdbus_sdhost;
|
||||
|
||||
uint8_t fsel[BCM2838_GPIO_NUM];
|
||||
uint32_t lev0, lev1;
|
||||
uint8_t sd_fsel;
|
||||
qemu_irq out[BCM2838_GPIO_NUM];
|
||||
uint32_t pup_cntrl_reg[GPIO_PUP_PDN_CNTRL_NUM];
|
||||
};
|
||||
|
||||
#endif
|
||||
Loading…
Add table
Add a link
Reference in a new issue