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target-arm queue:

Browse source 
* Handle atomic updates of page tables entries in MMIO during PTW
  * Advertise Cortex-A53 erratum #843419 fix via REVIDR
  * MAINTAINERS: Cover hw/ide/ahci-allwinner.c with AllWinner A10 machine
  * misc: m48t59: replace qemu_system_reset_request() call with watchdog_perform_action()
  * misc: pxa2xx_timer: replace qemu_system_reset_request() call with watchdog_perform_action()
  * xlnx-versal-ospi: disable reentrancy detection for iomem_dac
  * sbsa-ref: Simplify init since PCIe is always enabled
  * stm32l4x5: Use TYPE_OR_IRQ when connecting STM32L4x5 EXTI fan-in IRQs
  * pl031: Update last RTCLR value on write in case it's read back
  * block: m25p80: Add support of mt35xu02gbba
  * xlnx-versal-virt: Add machine property ospi-flash
  * reset: refactor system reset to be three-phase aware
  * new board model raspi4b
 -----BEGIN PGP SIGNATURE-----
 
 iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAmXeAMEZHHBldGVyLm1h
 eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3syyD/4lJzzstbDIAsu94Z4Hi0So
 CFLAMJFsPy3fMsU2IqVP+TDTyhUeMPebwfj7sQHUtQcXVh5i1/HlYgdUgXsnjGWQ
 pc6BxycpW6uJWYb7Ma3CdSGS+hxEpQ+U8Qeijwqg0kAqhjNtrSIkTRQ4u8p8T+kN
 dWtQzp7D15BpEVhWl/2dLWWJwV3H6TThmr1FbK5wl/c7hJzy2uaXqmmCvercU0Zo
 6ab3SnGyhaujdd/FsDvhnVEYqcmcO2p9UtSnGAbdfw0zsf4p8cS2Q6M9q4DHBFYn
 6Bt51DFP5D+114VpqRSXF2Lv9K8swjTgqhDld9vCoios6pS3LMwcTAcONUxE8JU+
 uD7kXTN/lv3atNEy4MTFkTeNtKgbYJJuPwWrDRNdbVXPwrEHGWN3+ZYISmuYb+p+
 XL2/7HeP7/qEVMW2d18+7OCriZwKiBRZRKUrtG7mQSBZEMetbhpA+mLcxAZT0FAl
 18O/mcvEJrrE7x6Bqyv96b8PE0/er5cVg/b/wrkKS8DL4NWU9bJSjJNRrvt9bvvl
 jSzPGo4ngHlfO0OpurLoFOZCVxKWVXgaKkQ3pOz301nsDyhEndNLeCxrITac8G2Q
 C/WQuMaeOoV1x7N2MzaCQmyRzy8yGkG9av0aI/8feobfV/Yg4wPsfhcEn/XQWXKv
 NUJ4/z78FbJlI2JeDP2QSA==
 =xaMv
 -----END PGP SIGNATURE-----

Merge tag 'pull-target-arm-20240227-1' of https://git.linaro.org/people/pmaydell/qemu-arm into staging

target-arm queue:
 * Handle atomic updates of page tables entries in MMIO during PTW
 * Advertise Cortex-A53 erratum #843419 fix via REVIDR
 * MAINTAINERS: Cover hw/ide/ahci-allwinner.c with AllWinner A10 machine
 * misc: m48t59: replace qemu_system_reset_request() call with watchdog_perform_action()
 * misc: pxa2xx_timer: replace qemu_system_reset_request() call with watchdog_perform_action()
 * xlnx-versal-ospi: disable reentrancy detection for iomem_dac
 * sbsa-ref: Simplify init since PCIe is always enabled
 * stm32l4x5: Use TYPE_OR_IRQ when connecting STM32L4x5 EXTI fan-in IRQs
 * pl031: Update last RTCLR value on write in case it's read back
 * block: m25p80: Add support of mt35xu02gbba
 * xlnx-versal-virt: Add machine property ospi-flash
 * reset: refactor system reset to be three-phase aware
 * new board model raspi4b

# -----BEGIN PGP SIGNATURE-----
#
# iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAmXeAMEZHHBldGVyLm1h
# eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3syyD/4lJzzstbDIAsu94Z4Hi0So
# CFLAMJFsPy3fMsU2IqVP+TDTyhUeMPebwfj7sQHUtQcXVh5i1/HlYgdUgXsnjGWQ
# pc6BxycpW6uJWYb7Ma3CdSGS+hxEpQ+U8Qeijwqg0kAqhjNtrSIkTRQ4u8p8T+kN
# dWtQzp7D15BpEVhWl/2dLWWJwV3H6TThmr1FbK5wl/c7hJzy2uaXqmmCvercU0Zo
# 6ab3SnGyhaujdd/FsDvhnVEYqcmcO2p9UtSnGAbdfw0zsf4p8cS2Q6M9q4DHBFYn
# 6Bt51DFP5D+114VpqRSXF2Lv9K8swjTgqhDld9vCoios6pS3LMwcTAcONUxE8JU+
# uD7kXTN/lv3atNEy4MTFkTeNtKgbYJJuPwWrDRNdbVXPwrEHGWN3+ZYISmuYb+p+
# XL2/7HeP7/qEVMW2d18+7OCriZwKiBRZRKUrtG7mQSBZEMetbhpA+mLcxAZT0FAl
# 18O/mcvEJrrE7x6Bqyv96b8PE0/er5cVg/b/wrkKS8DL4NWU9bJSjJNRrvt9bvvl
# jSzPGo4ngHlfO0OpurLoFOZCVxKWVXgaKkQ3pOz301nsDyhEndNLeCxrITac8G2Q
# C/WQuMaeOoV1x7N2MzaCQmyRzy8yGkG9av0aI/8feobfV/Yg4wPsfhcEn/XQWXKv
# NUJ4/z78FbJlI2JeDP2QSA==
# =xaMv
# -----END PGP SIGNATURE-----
# gpg: Signature made Tue 27 Feb 2024 15:33:21 GMT
# gpg:                using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg:                issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate]
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>" [ultimate]
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate]
# gpg:                 aka "Peter Maydell <peter@archaic.org.uk>" [ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* tag 'pull-target-arm-20240227-1' of https://git.linaro.org/people/pmaydell/qemu-arm: (36 commits)
  docs/system/arm: Add RPi4B to raspi.rst
  hw/misc/bcm2835_property: Add missed BCM2835 properties
  tests/avocado/boot_linux_console.py: Add Rpi4b boot tests
  hw/arm/bcm2838_peripherals: Add clock_isp stub
  hw/arm: Add memory region for BCM2837 RPiVid ASB
  hw/arm/raspi4b: Temporarily disable unimplemented rpi4b devices
  hw/arm: Introduce Raspberry PI 4 machine
  hw/arm: Add GPIO and SD to BCM2838 periph
  hw/gpio: Connect SD controller to BCM2838 GPIO
  hw/gpio: Implement BCM2838 GPIO functionality
  hw/gpio: Add BCM2838 GPIO stub
  hw/arm/bcm2838: Add GIC-400 to BCM2838 SoC
  hw/arm: Introduce BCM2838 SoC
  hw/arm/raspi: Split out raspi machine common part
  hw/arm/bcm2853_peripherals: Split out common part of peripherals
  hw/arm/bcm2836: Split out common part of BCM283X classes
  docs/devel/reset: Update to discuss system reset
  hw/core/machine: Use qemu_register_resettable for sysbus reset
  hw/core/reset: Implement qemu_register_reset via qemu_register_resettable
  hw/core/reset: Add qemu_{register, unregister}_resettable()
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell 2024-02-27 15:34:41 +00:00
commit 158a054c4d
46 changed files with 2503 additions and 305 deletions
Download patch file Download diff file Expand all files Collapse all files

29
include/hw/arm/bcm2835_peripherals.h
View file

@ -35,10 +35,13 @@
#include "hw/misc/unimp.h"
#include "qom/object.h"
#define TYPE_BCM_SOC_PERIPHERALS_BASE "bcm-soc-peripherals-base"
OBJECT_DECLARE_TYPE(BCMSocPeripheralBaseState, BCMSocPeripheralBaseClass,
BCM_SOC_PERIPHERALS_BASE)
#define TYPE_BCM2835_PERIPHERALS "bcm2835-peripherals"
OBJECT_DECLARE_SIMPLE_TYPE(BCM2835PeripheralState, BCM2835_PERIPHERALS)
struct BCM2835PeripheralState {
struct BCMSocPeripheralBaseState {
/*< private >*/
SysBusDevice parent_obj;
/*< public >*/
@ -60,12 +63,9 @@ struct BCM2835PeripheralState {
OrIRQState orgated_dma_irq;
BCM2835ICState ic;
BCM2835PropertyState property;
BCM2835RngState rng;
BCM2835MboxState mboxes;
SDHCIState sdhci;
BCM2835SDHostState sdhost;
BCM2835GpioState gpio;
Bcm2835ThermalState thermal;
UnimplementedDeviceState i2s;
BCM2835SPIState spi[1];
UnimplementedDeviceState i2c[3];
@ -79,4 +79,25 @@ struct BCM2835PeripheralState {
UnimplementedDeviceState sdramc;
};
struct BCMSocPeripheralBaseClass {
/*< private >*/
SysBusDeviceClass parent_class;
/*< public >*/
uint64_t peri_size; /* Peripheral range size */
};
struct BCM2835PeripheralState {
/*< private >*/
BCMSocPeripheralBaseState parent_obj;
/*< public >*/
BCM2835RngState rng;
Bcm2835ThermalState thermal;
BCM2835GpioState gpio;
};
void create_unimp(BCMSocPeripheralBaseState *ps,
UnimplementedDeviceState *uds,
const char *name, hwaddr ofs, hwaddr size);
void bcm_soc_peripherals_common_realize(DeviceState *dev, Error **errp);
#endif /* BCM2835_PERIPHERALS_H */

27
include/hw/arm/bcm2836.h
View file

@ -17,8 +17,10 @@
#include "target/arm/cpu.h"
#include "qom/object.h"
#define TYPE_BCM283X_BASE "bcm283x-base"
OBJECT_DECLARE_TYPE(BCM283XBaseState, BCM283XBaseClass, BCM283X_BASE)
#define TYPE_BCM283X "bcm283x"
OBJECT_DECLARE_TYPE(BCM283XState, BCM283XClass, BCM283X)
OBJECT_DECLARE_SIMPLE_TYPE(BCM283XState, BCM283X)
#define BCM283X_NCPUS 4
@ -30,7 +32,7 @@ OBJECT_DECLARE_TYPE(BCM283XState, BCM283XClass, BCM283X)
#define TYPE_BCM2836 "bcm2836"
#define TYPE_BCM2837 "bcm2837"
struct BCM283XState {
struct BCM283XBaseState {
/*< private >*/
DeviceState parent_obj;
/*< public >*/
@ -41,7 +43,28 @@ struct BCM283XState {
ARMCPU core;
} cpu[BCM283X_NCPUS];
BCM2836ControlState control;
};
struct BCM283XBaseClass {
/*< private >*/
DeviceClass parent_class;
/*< public >*/
const char *name;
const char *cpu_type;
unsigned core_count;
hwaddr peri_base; /* Peripheral base address seen by the CPU */
hwaddr ctrl_base; /* Interrupt controller and mailboxes etc. */
int clusterid;
};
struct BCM283XState {
/*< private >*/
BCM283XBaseState parent_obj;
/*< public >*/
BCM2835PeripheralState peripherals;
};
bool bcm283x_common_realize(DeviceState *dev, BCMSocPeripheralBaseState *ps,
Error **errp);
#endif /* BCM2836_H */

31
include/hw/arm/bcm2838.h Normal file
View file

@ -0,0 +1,31 @@
/*
* BCM2838 SoC emulation
*
* Copyright (C) 2022 Ovchinnikov Vitalii <vitalii.ovchinnikov@auriga.com>
*
* SPDX-License-Identifier: GPL-2.0-or-later
*/
#ifndef BCM2838_H
#define BCM2838_H
#include "hw/arm/bcm2836.h"
#include "hw/intc/arm_gic.h"
#include "hw/arm/bcm2838_peripherals.h"
#define BCM2838_PERI_LOW_BASE 0xfc000000
#define BCM2838_GIC_BASE 0x40000
#define TYPE_BCM2838 "bcm2838"
OBJECT_DECLARE_TYPE(BCM2838State, BCM2838Class, BCM2838)
struct BCM2838State {
/*< private >*/
BCM283XBaseState parent_obj;
/*< public >*/
BCM2838PeripheralState peripherals;
GICState gic;
};
#endif /* BCM2838_H */

84
include/hw/arm/bcm2838_peripherals.h Normal file
View file

@ -0,0 +1,84 @@
/*
* BCM2838 peripherals emulation
*
* Copyright (C) 2022 Ovchinnikov Vitalii <vitalii.ovchinnikov@auriga.com>
*
* SPDX-License-Identifier: GPL-2.0-or-later
*/
#ifndef BCM2838_PERIPHERALS_H
#define BCM2838_PERIPHERALS_H
#include "hw/arm/bcm2835_peripherals.h"
#include "hw/sd/sdhci.h"
#include "hw/gpio/bcm2838_gpio.h"
/* SPI */
#define GIC_SPI_INTERRUPT_MBOX 33
#define GIC_SPI_INTERRUPT_MPHI 40
#define GIC_SPI_INTERRUPT_DWC2 73
#define GIC_SPI_INTERRUPT_DMA_0 80
#define GIC_SPI_INTERRUPT_DMA_6 86
#define GIC_SPI_INTERRUPT_DMA_7_8 87
#define GIC_SPI_INTERRUPT_DMA_9_10 88
#define GIC_SPI_INTERRUPT_AUX_UART1 93
#define GIC_SPI_INTERRUPT_SDHOST 120
#define GIC_SPI_INTERRUPT_UART0 121
#define GIC_SPI_INTERRUPT_RNG200 125
#define GIC_SPI_INTERRUPT_EMMC_EMMC2 126
#define GIC_SPI_INTERRUPT_PCI_INT_A 143
#define GIC_SPI_INTERRUPT_GENET_A 157
#define GIC_SPI_INTERRUPT_GENET_B 158
/* GPU (legacy) DMA interrupts */
#define GPU_INTERRUPT_DMA0 16
#define GPU_INTERRUPT_DMA1 17
#define GPU_INTERRUPT_DMA2 18
#define GPU_INTERRUPT_DMA3 19
#define GPU_INTERRUPT_DMA4 20
#define GPU_INTERRUPT_DMA5 21
#define GPU_INTERRUPT_DMA6 22
#define GPU_INTERRUPT_DMA7_8 23
#define GPU_INTERRUPT_DMA9_10 24
#define GPU_INTERRUPT_DMA11 25
#define GPU_INTERRUPT_DMA12 26
#define GPU_INTERRUPT_DMA13 27
#define GPU_INTERRUPT_DMA14 28
#define GPU_INTERRUPT_DMA15 31
#define BCM2838_MPHI_OFFSET 0xb200
#define BCM2838_MPHI_SIZE 0x200
#define TYPE_BCM2838_PERIPHERALS "bcm2838-peripherals"
OBJECT_DECLARE_TYPE(BCM2838PeripheralState, BCM2838PeripheralClass,
BCM2838_PERIPHERALS)
struct BCM2838PeripheralState {
/*< private >*/
BCMSocPeripheralBaseState parent_obj;
/*< public >*/
MemoryRegion peri_low_mr;
MemoryRegion peri_low_mr_alias;
MemoryRegion mphi_mr_alias;
SDHCIState emmc2;
BCM2838GpioState gpio;
OrIRQState mmc_irq_orgate;
OrIRQState dma_7_8_irq_orgate;
OrIRQState dma_9_10_irq_orgate;
UnimplementedDeviceState asb;
UnimplementedDeviceState clkisp;
};
struct BCM2838PeripheralClass {
/*< private >*/
BCMSocPeripheralBaseClass parent_class;
/*< public >*/
uint64_t peri_low_size; /* Peripheral lower range size */
};
#endif /* BCM2838_PERIPHERALS_H */

11
include/hw/arm/raspberrypi-fw-defs.h
View file

@ -159,4 +159,15 @@ enum rpi_firmware_clk_id {
RPI_FIRMWARE_NUM_CLK_ID,
};
struct rpi_firmware_property_tag_header {
uint32_t tag;
uint32_t buf_size;
uint32_t req_resp_size;
};
typedef struct rpi_firmware_prop_request {
struct rpi_firmware_property_tag_header hdr;
uint8_t payload[0];
} rpi_firmware_prop_request_t;
#endif /* INCLUDE_HW_MISC_RASPBERRYPI_FW_DEFS_H_ */

38
include/hw/arm/raspi_platform.h
View file

@ -28,6 +28,42 @@
#ifndef HW_ARM_RASPI_PLATFORM_H
#define HW_ARM_RASPI_PLATFORM_H
#include "hw/boards.h"
#include "hw/arm/boot.h"
/* Registered machine type (matches RPi Foundation bootloader and U-Boot) */
#define MACH_TYPE_BCM2708 3138
#define TYPE_RASPI_BASE_MACHINE MACHINE_TYPE_NAME("raspi-base")
OBJECT_DECLARE_TYPE(RaspiBaseMachineState, RaspiBaseMachineClass,
RASPI_BASE_MACHINE)
struct RaspiBaseMachineState {
/*< private >*/
MachineState parent_obj;
/*< public >*/
struct arm_boot_info binfo;
};
struct RaspiBaseMachineClass {
/*< private >*/
MachineClass parent_obj;
/*< public >*/
uint32_t board_rev;
};
/* Common functions for raspberry pi machines */
const char *board_soc_type(uint32_t board_rev);
void raspi_machine_init(MachineState *machine);
typedef struct BCM283XBaseState BCM283XBaseState;
void raspi_base_machine_init(MachineState *machine,
BCM283XBaseState *soc);
void raspi_machine_class_common_init(MachineClass *mc,
uint32_t board_rev);
uint64_t board_ram_size(uint32_t board_rev);
#define MSYNC_OFFSET 0x0000 /* Multicore Sync Block */
#define CCPT_OFFSET 0x1000 /* Compact Camera Port 2 TX */
#define INTE_OFFSET 0x2000 /* VC Interrupt controller */
@ -37,7 +73,7 @@
#define MPHI_OFFSET 0x6000 /* Message-based Parallel Host Intf. */
#define DMA_OFFSET 0x7000 /* DMA controller, channels 0-14 */
#define ARBA_OFFSET 0x9000
#define BRDG_OFFSET 0xa000
#define BRDG_OFFSET 0xa000 /* RPiVid ASB for BCM2838 (BCM2711) */
#define ARM_OFFSET 0xB000 /* ARM control block */
#define ARMCTRL_OFFSET (ARM_OFFSET + 0x000)
#define ARMCTRL_IC_OFFSET (ARM_OFFSET + 0x200) /* Interrupt controller */

4
include/hw/arm/stm32l4x5_soc.h
View file

@ -26,6 +26,7 @@
#include "exec/memory.h"
#include "hw/arm/armv7m.h"
#include "hw/or-irq.h"
#include "hw/misc/stm32l4x5_syscfg.h"
#include "hw/misc/stm32l4x5_exti.h"
#include "qom/object.h"
@ -36,12 +37,15 @@
#define TYPE_STM32L4X5XG_SOC "stm32l4x5xg-soc"
OBJECT_DECLARE_TYPE(Stm32l4x5SocState, Stm32l4x5SocClass, STM32L4X5_SOC)
#define NUM_EXTI_OR_GATES 4
struct Stm32l4x5SocState {
SysBusDevice parent_obj;
ARMv7MState armv7m;
Stm32l4x5ExtiState exti;
OrIRQState exti_or_gates[NUM_EXTI_OR_GATES];
Stm32l4x5SyscfgState syscfg;
MemoryRegion sram1;

48
include/hw/core/resetcontainer.h Normal file
View file

@ -0,0 +1,48 @@
/*
* Reset container
*
* Copyright (c) 2024 Linaro, Ltd
*
* This work is licensed under the terms of the GNU GPL, version 2 or later.
* See the COPYING file in the top-level directory.
*/
#ifndef HW_RESETCONTAINER_H
#define HW_RESETCONTAINER_H
/*
* The "reset container" is an object which implements the Resettable
* interface. It contains a list of arbitrary other objects which also
* implement Resettable. Resetting the reset container resets all the
* objects in it.
*/
#include "qom/object.h"
#define TYPE_RESETTABLE_CONTAINER "resettable-container"
OBJECT_DECLARE_TYPE(ResettableContainer, ResettableContainerClass, RESETTABLE_CONTAINER)
/**
* resettable_container_add: Add a resettable object to the container
* @rc: container
* @obj: object to add to the container
*
* Add @obj to the ResettableContainer @rc. @obj must implement the
* Resettable interface.
*
* When @rc is reset, it will reset every object that has been added
* to it, in the order they were added.
*/
void resettable_container_add(ResettableContainer *rc, Object *obj);
/**
* resettable_container_remove: Remove an object from the container
* @rc: container
* @obj: object to remove from the container
*
* Remove @obj from the ResettableContainer @rc. @obj must have been
* previously added to this container.
*/
void resettable_container_remove(ResettableContainer *rc, Object *obj);
#endif

2
include/hw/display/bcm2835_fb.h
View file

@ -16,6 +16,8 @@
#include "ui/console.h"
#include "qom/object.h"
#define UPPER_RAM_BASE 0x40000000
#define TYPE_BCM2835_FB "bcm2835-fb"
OBJECT_DECLARE_SIMPLE_TYPE(BCM2835FBState, BCM2835_FB)

45
include/hw/gpio/bcm2838_gpio.h Normal file
View file

@ -0,0 +1,45 @@
/*
* Raspberry Pi (BCM2838) GPIO Controller
* This implementation is based on bcm2835_gpio (hw/gpio/bcm2835_gpio.c)
*
* Copyright (c) 2022 Auriga LLC
*
* Authors:
* Lotosh, Aleksey <aleksey.lotosh@auriga.com>
*
* This work is licensed under the terms of the GNU GPL, version 2 or later.
* See the COPYING file in the top-level directory.
*/
#ifndef BCM2838_GPIO_H
#define BCM2838_GPIO_H
#include "hw/sd/sd.h"
#include "hw/sysbus.h"
#include "qom/object.h"
#define TYPE_BCM2838_GPIO "bcm2838-gpio"
OBJECT_DECLARE_SIMPLE_TYPE(BCM2838GpioState, BCM2838_GPIO)
#define BCM2838_GPIO_REGS_SIZE 0x1000
#define BCM2838_GPIO_NUM 58
#define GPIO_PUP_PDN_CNTRL_NUM 4
struct BCM2838GpioState {
SysBusDevice parent_obj;
MemoryRegion iomem;
/* SDBus selector */
SDBus sdbus;
SDBus *sdbus_sdhci;
SDBus *sdbus_sdhost;
uint8_t fsel[BCM2838_GPIO_NUM];
uint32_t lev0, lev1;
uint8_t sd_fsel;
qemu_irq out[BCM2838_GPIO_NUM];
uint32_t pup_cntrl_reg[GPIO_PUP_PDN_CNTRL_NUM];
};
#endif

114
include/qom/object.h
View file

@ -258,6 +258,51 @@ struct Object
DECLARE_INSTANCE_CHECKER(InstanceType, MODULE_OBJ_NAME, TYPE_##MODULE_OBJ_NAME)
/**
* DO_OBJECT_DEFINE_TYPE_EXTENDED:
* @ModuleObjName: the object name with initial caps
* @module_obj_name: the object name in lowercase with underscore separators
* @MODULE_OBJ_NAME: the object name in uppercase with underscore separators
* @PARENT_MODULE_OBJ_NAME: the parent object name in uppercase with underscore
* separators
* @ABSTRACT: boolean flag to indicate whether the object can be instantiated
* @CLASS_SIZE: size of the type's class
* @...: list of initializers for "InterfaceInfo" to declare implemented interfaces
*
* This is the base macro used to implement all the OBJECT_DEFINE_*
* macros. It should never be used directly in a source file.
*/
#define DO_OBJECT_DEFINE_TYPE_EXTENDED(ModuleObjName, module_obj_name, \
MODULE_OBJ_NAME, \
PARENT_MODULE_OBJ_NAME, \
ABSTRACT, CLASS_SIZE, ...) \
static void \
module_obj_name##_finalize(Object *obj); \
static void \
module_obj_name##_class_init(ObjectClass *oc, void *data); \
static void \
module_obj_name##_init(Object *obj); \
\
static const TypeInfo module_obj_name##_info = { \
.parent = TYPE_##PARENT_MODULE_OBJ_NAME, \
.name = TYPE_##MODULE_OBJ_NAME, \
.instance_size = sizeof(ModuleObjName), \
.instance_align = __alignof__(ModuleObjName), \
.instance_init = module_obj_name##_init, \
.instance_finalize = module_obj_name##_finalize, \
.class_size = CLASS_SIZE, \
.class_init = module_obj_name##_class_init, \
.abstract = ABSTRACT, \
.interfaces = (InterfaceInfo[]) { __VA_ARGS__ } , \
}; \
\
static void \
module_obj_name##_register_types(void) \
{ \
type_register_static(&module_obj_name##_info); \
} \
type_init(module_obj_name##_register_types);
/**
* OBJECT_DEFINE_TYPE_EXTENDED:
* @ModuleObjName: the object name with initial caps
@ -284,32 +329,10 @@ struct Object
#define OBJECT_DEFINE_TYPE_EXTENDED(ModuleObjName, module_obj_name, \
MODULE_OBJ_NAME, PARENT_MODULE_OBJ_NAME, \
ABSTRACT, ...) \
static void \
module_obj_name##_finalize(Object *obj); \
static void \
module_obj_name##_class_init(ObjectClass *oc, void *data); \
static void \
module_obj_name##_init(Object *obj); \
\
static const TypeInfo module_obj_name##_info = { \
.parent = TYPE_##PARENT_MODULE_OBJ_NAME, \
.name = TYPE_##MODULE_OBJ_NAME, \
.instance_size = sizeof(ModuleObjName), \
.instance_align = __alignof__(ModuleObjName), \
.instance_init = module_obj_name##_init, \
.instance_finalize = module_obj_name##_finalize, \
.class_size = sizeof(ModuleObjName##Class), \
.class_init = module_obj_name##_class_init, \
.abstract = ABSTRACT, \
.interfaces = (InterfaceInfo[]) { __VA_ARGS__ } , \
}; \
\
static void \
module_obj_name##_register_types(void) \
{ \
type_register_static(&module_obj_name##_info); \
} \
type_init(module_obj_name##_register_types);
DO_OBJECT_DEFINE_TYPE_EXTENDED(ModuleObjName, module_obj_name, \
MODULE_OBJ_NAME, PARENT_MODULE_OBJ_NAME, \
ABSTRACT, sizeof(ModuleObjName##Class), \
__VA_ARGS__)
/**
* OBJECT_DEFINE_TYPE:
@ -368,6 +391,45 @@ struct Object
MODULE_OBJ_NAME, PARENT_MODULE_OBJ_NAME, \
true, { NULL })
/**
* OBJECT_DEFINE_SIMPLE_TYPE_WITH_INTERFACES:
* @ModuleObjName: the object name with initial caps
* @module_obj_name: the object name in lowercase with underscore separators
* @MODULE_OBJ_NAME: the object name in uppercase with underscore separators
* @PARENT_MODULE_OBJ_NAME: the parent object name in uppercase with underscore
* separators
*
* This is a variant of OBJECT_DEFINE_TYPE_EXTENDED, which is suitable for
* the case of a non-abstract type, with interfaces, and with no requirement
* for a class struct.
*/
#define OBJECT_DEFINE_SIMPLE_TYPE_WITH_INTERFACES(ModuleObjName, \
module_obj_name, \
MODULE_OBJ_NAME, \
PARENT_MODULE_OBJ_NAME, ...) \
DO_OBJECT_DEFINE_TYPE_EXTENDED(ModuleObjName, module_obj_name, \
MODULE_OBJ_NAME, PARENT_MODULE_OBJ_NAME, \
false, 0, __VA_ARGS__)
/**
* OBJECT_DEFINE_SIMPLE_TYPE:
* @ModuleObjName: the object name with initial caps
* @module_obj_name: the object name in lowercase with underscore separators
* @MODULE_OBJ_NAME: the object name in uppercase with underscore separators
* @PARENT_MODULE_OBJ_NAME: the parent object name in uppercase with underscore
* separators
*
* This is a variant of OBJECT_DEFINE_TYPE_EXTENDED, which is suitable for
* the common case of a non-abstract type, without any interfaces, and with
* no requirement for a class struct. If you declared your type with
* OBJECT_DECLARE_SIMPLE_TYPE then this is probably the right choice for
* defining it.
*/
#define OBJECT_DEFINE_SIMPLE_TYPE(ModuleObjName, module_obj_name, \
MODULE_OBJ_NAME, PARENT_MODULE_OBJ_NAME) \
OBJECT_DEFINE_SIMPLE_TYPE_WITH_INTERFACES(ModuleObjName, module_obj_name, \
MODULE_OBJ_NAME, PARENT_MODULE_OBJ_NAME, { NULL })
/**
* struct TypeInfo:
* @name: The name of the type.

113
include/sysemu/reset.h
View file

@ -1,3 +1,29 @@
/*
* Reset handlers.
*
* Copyright (c) 2003-2008 Fabrice Bellard
* Copyright (c) 2016 Red Hat, Inc.
* Copyright (c) 2024 Linaro, Ltd.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
#ifndef QEMU_SYSEMU_RESET_H
#define QEMU_SYSEMU_RESET_H
@ -5,9 +31,96 @@
typedef void QEMUResetHandler(void *opaque);
/**
* qemu_register_resettable: Register an object to be reset
* @obj: object to be reset: it must implement the Resettable interface
*
* Register @obj on the list of objects which will be reset when the
* simulation is reset. These objects will be reset in the order
* they were added, using the three-phase Resettable protocol,
* so first all objects go through the enter phase, then all objects
* go through the hold phase, and then finally all go through the
* exit phase.
*
* It is not permitted to register or unregister reset functions or
* resettable objects from within any of the reset phase methods of @obj.
*
* We assume that the caller holds the BQL.
*/
void qemu_register_resettable(Object *obj);
/**
* qemu_unregister_resettable: Unregister an object to be reset
* @obj: object to unregister
*
* Remove @obj from the list of objects which are reset when the
* simulation is reset. It must have been previously added to
* the list via qemu_register_resettable().
*
* We assume that the caller holds the BQL.
*/
void qemu_unregister_resettable(Object *obj);
/**
* qemu_register_reset: Register a callback for system reset
* @func: function to call
* @opaque: opaque data to pass to @func
*
* Register @func on the list of functions which are called when the
* entire system is reset. Functions registered with this API and
* Resettable objects registered with qemu_register_resettable() are
* handled together, in the order in which they were registered.
* Functions registered with this API are called in the 'hold' phase
* of the 3-phase reset.
*
* In general this function should not be used in new code where possible;
* for instance, device model reset is better accomplished using the
* methods on DeviceState.
*
* It is not permitted to register or unregister reset functions or
* resettable objects from within the @func callback.
*
* We assume that the caller holds the BQL.
*/
void qemu_register_reset(QEMUResetHandler *func, void *opaque);
/**
* qemu_register_reset_nosnapshotload: Register a callback for system reset
* @func: function to call
* @opaque: opaque data to pass to @func
*
* This is the same as qemu_register_reset(), except that @func is
* not called if the reason that the system is being reset is to
* put it into a clean state prior to loading a snapshot (i.e. for
* SHUTDOWN_CAUSE_SNAPSHOT_LOAD).
*/
void qemu_register_reset_nosnapshotload(QEMUResetHandler *func, void *opaque);
/**
* qemu_unregister_reset: Unregister a system reset callback
* @func: function registered with qemu_register_reset()
* @opaque: the same opaque data that was passed to qemu_register_reset()
*
* Undo the effects of a qemu_register_reset(). The @func and @opaque
* must both match the arguments originally used with qemu_register_reset().
*
* We assume that the caller holds the BQL.
*/
void qemu_unregister_reset(QEMUResetHandler *func, void *opaque);
/**
* qemu_devices_reset: Perform a complete system reset
* @reason: reason for the reset
*
* This function performs the low-level work needed to do a complete reset
* of the system (calling all the callbacks registered with
* qemu_register_reset() and resetting all the Resettable objects registered
* with qemu_register_resettable()). It should only be called by the code in a
* MachineClass reset method.
*
* If you want to trigger a system reset from, for instance, a device
* model, don't use this function. Use qemu_system_reset_request().
*/
void qemu_devices_reset(ShutdownCause reason);
#endif