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target/arm: Convert T16, shift immediate

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Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20190904193059.26202-65-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson 2019-09-04 12:30:54 -07:00 • committed by Peter Maydell
parent 43f7e42c7d
commit 151c2f2841
2 changed files with 10 additions and 24 deletions
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8
target/arm/t16.decode
View file

@ -126,6 +126,14 @@ ADD_rri 10101 rd:3 ........ \
STM 11000 ... ........ @ldstm STM 11000 ... ........ @ldstm
LDM_t16 11001 ... ........ @ldstm LDM_t16 11001 ... ........ @ldstm
# Shift (immediate)
@shift_i ..... shim:5 rm:3 rd:3 &s_rrr_shi %s rn=%reg_0
MOV_rxri 000 00 ..... ... ... @shift_i shty=0 # LSL
MOV_rxri 000 01 ..... ... ... @shift_i shty=1 # LSR
MOV_rxri 000 10 ..... ... ... @shift_i shty=2 # ASR
# Add/subtract (three low registers) # Add/subtract (three low registers)
@addsub_3 ....... rm:3 rn:3 rd:3 \ @addsub_3 ....... rm:3 rn:3 rd:3 \

26
target/arm/translate.c
View file

@ -10754,7 +10754,7 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
static void disas_thumb_insn(DisasContext *s, uint32_t insn) static void disas_thumb_insn(DisasContext *s, uint32_t insn)
{ {
uint32_t val, op, rm, rd, shift; uint32_t val, rd;
int32_t offset; int32_t offset;
TCGv_i32 tmp; TCGv_i32 tmp;
TCGv_i32 tmp2; TCGv_i32 tmp2;
@ -10766,29 +10766,7 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn)
/* fall back to legacy decoder */ /* fall back to legacy decoder */
switch (insn >> 12) { switch (insn >> 12) {
case 0: case 1: case 0: case 1: /* add/sub (3reg, 2reg imm), shift imm; in decodetree */
rd = insn & 7;
op = (insn >> 11) & 3;
if (op == 3) {
/*
* 0b0001_1xxx_xxxx_xxxx
* - Add, subtract (three low registers)
* - Add, subtract (two low registers and immediate)
* In decodetree.
*/
goto illegal_op;
} else {
/* shift immediate */
rm = (insn >> 3) & 7;
shift = (insn >> 6) & 0x1f;
tmp = load_reg(s, rm);
gen_arm_shift_im(tmp, op, shift, s->condexec_mask == 0);
if (!s->condexec_mask)
gen_logic_CC(tmp);
store_reg(s, rd, tmp);
}
break;
case 2: case 3: /* add, sub, cmp, mov (reg, imm), in decodetree */ case 2: case 3: /* add, sub, cmp, mov (reg, imm), in decodetree */
goto illegal_op; goto illegal_op;
case 4: case 4: