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target/riscv: Don't clear mask in riscv_cpu_update_mip() for VSTIP

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Instead of clearing mask in riscv_cpu_update_mip() for VSTIP, we
should call riscv_cpu_update_mip() with mask == 0 from timer_helper.c
for VSTIP.

Fixes: 3ec0fe18a3 ("target/riscv: Add vstimecmp suppor")
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230120125950.2246378-3-apatel@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Anup Patel 2023-01-20 18:29:48 +05:30 • committed by Alistair Francis
parent 2cfb3b6c9b
commit 14cb78bfaf
2 changed files with 8 additions and 6 deletions
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12
target/riscv/time_helper.c
View file

@ -27,7 +27,7 @@ static void riscv_vstimer_cb(void *opaque)
RISCVCPU *cpu = opaque;
CPURISCVState *env = &cpu->env;
env->vstime_irq = 1;
riscv_cpu_update_mip(cpu, MIP_VSTIP, BOOL_TO_MASK(1));
riscv_cpu_update_mip(cpu, 0, BOOL_TO_MASK(1));
}
static void riscv_stimer_cb(void *opaque)
@ -57,16 +57,20 @@ void riscv_timer_write_timecmp(RISCVCPU *cpu, QEMUTimer *timer,
*/
if (timer_irq == MIP_VSTIP) {
env->vstime_irq = 1;
riscv_cpu_update_mip(cpu, 0, BOOL_TO_MASK(1));
} else {
riscv_cpu_update_mip(cpu, MIP_STIP, BOOL_TO_MASK(1));
}
riscv_cpu_update_mip(cpu, timer_irq, BOOL_TO_MASK(1));
return;
}
/* Clear the [VS|S]TIP bit in mip */
if (timer_irq == MIP_VSTIP) {
env->vstime_irq = 0;
riscv_cpu_update_mip(cpu, 0, BOOL_TO_MASK(0));
} else {
riscv_cpu_update_mip(cpu, timer_irq, BOOL_TO_MASK(0));
}
/* Clear the [V]STIP bit in mip */
riscv_cpu_update_mip(cpu, timer_irq, BOOL_TO_MASK(0));
/* otherwise, set up the future timer interrupt */
diff = timecmp - rtc_r;