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target-arm queue:

Browse source 
* add virtio-mmio transport base address to device path
    (avoid an assertion failure with multiple virtio-scsi-devices)
  * revert hw/ptimer commit 5a50307 which causes regressions on
    SPARC guests
  * use Neon to accelerate zero-page checking on AArch64 hosts
  * set the MPIDR for TCG to match how KVM does it (and fit with
    GICv2/GICv3 restrictions on SGI target lists)
  * add some missing AArch32 TLBI hypervisor TLB operations
  * m25p80: Fix QIOR/DIOR handling for Winbond
  * hw/misc: fix typo in Aspeed SCU hw-strap2 property name
  * ast2400: pretend DMAs are done for U-boot
  * ast2400: some minor code cleanups
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Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20160714' into staging

target-arm queue:
 * add virtio-mmio transport base address to device path
   (avoid an assertion failure with multiple virtio-scsi-devices)
 * revert hw/ptimer commit 5a50307 which causes regressions on
   SPARC guests
 * use Neon to accelerate zero-page checking on AArch64 hosts
 * set the MPIDR for TCG to match how KVM does it (and fit with
   GICv2/GICv3 restrictions on SGI target lists)
 * add some missing AArch32 TLBI hypervisor TLB operations
 * m25p80: Fix QIOR/DIOR handling for Winbond
 * hw/misc: fix typo in Aspeed SCU hw-strap2 property name
 * ast2400: pretend DMAs are done for U-boot
 * ast2400: some minor code cleanups

# gpg: Signature made Thu 14 Jul 2016 17:21:30 BST
# gpg:                using RSA key 0x3C2525ED14360CDE
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>"
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>"
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>"
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* remotes/pmaydell/tags/pull-target-arm-20160714:
  ast2400: externalize revision numbers
  ast2400: pretend DMAs are done for U-boot
  ast2400: replace aspeed_smc_is_implemented()
  hw/misc: fix typo in Aspeed SCU hw-strap2 property name
  m25p80: Fix QIOR/DIOR handling for Winbond
  target-arm: Add missed AArch32 TLBI sytem registers
  hw/arm/virt: tcg: adjust MPIDR like KVM
  gic: provide defines for v2/v3 targetlist sizes
  target-arm: Use Neon for zero checking
  Revert "hw/ptimer: Perform counter wrap around if timer already expired"
  virtio-mmio: format transport base address in BusClass.get_dev_path

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell 2016-07-14 17:32:53 +01:00
commit 14c7d99333
13 changed files with 262 additions and 37 deletions
Download patch file Download diff file Expand all files Collapse all files

6
include/hw/compat.h
View file

@ -2,7 +2,11 @@
#define HW_COMPAT_H
#define HW_COMPAT_2_6 \
/* empty */
{\
.driver = "virtio-mmio",\
.property = "format_transport_address",\
.value = "off",\
},
#define HW_COMPAT_2_5 \
{\

3
include/hw/intc/arm_gic.h
View file

@ -23,6 +23,9 @@
#include "arm_gic_common.h"
/* Number of SGI target-list bits */
#define GIC_TARGETLIST_BITS 8
#define TYPE_ARM_GIC "arm_gic"
#define ARM_GIC(obj) \
OBJECT_CHECK(GICState, (obj), TYPE_ARM_GIC)

3
include/hw/intc/arm_gicv3_common.h
View file

@ -35,6 +35,9 @@
#define GICV3_MAXIRQ 1020
#define GICV3_MAXSPI (GICV3_MAXIRQ - GIC_INTERNAL)
/* Number of SGI target-list bits */
#define GICV3_TARGETLIST_BITS 16
/* Minimum BPR for Secure, or when security not enabled */
#define GIC_MIN_BPR 0
/* Minimum BPR for Nonsecure when security is enabled */

5
include/hw/misc/aspeed_scu.h
View file

@ -31,4 +31,9 @@ typedef struct AspeedSCUState {
uint32_t hw_strap2;
} AspeedSCUState;
#define AST2400_A0_SILICON_REV 0x02000303U
#define AST2500_A0_SILICON_REV 0x04000303U
extern bool is_supported_silicon_rev(uint32_t silicon_rev);
#endif /* ASPEED_SCU_H */