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target/arm: Add arm_tlb_bti_gp

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Introduce an lvalue macro to wrap target_tlb_bit0.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200626033144.790098-33-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson 2020-06-25 20:31:30 -07:00 • committed by Peter Maydell
parent c0ed9166b1
commit 149d3b31f3
3 changed files with 15 additions and 2 deletions
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13
target/arm/cpu.h
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@ -3393,6 +3393,19 @@ static inline uint64_t *aa64_vfp_qreg(CPUARMState *env, unsigned regno)
/* Shared between translate-sve.c and sve_helper.c. */
extern const uint64_t pred_esz_masks[4];
/* Helper for the macros below, validating the argument type. */
static inline MemTxAttrs *typecheck_memtxattrs(MemTxAttrs *x)
{
return x;
}
/*
* Lvalue macros for ARM TLB bits that we must cache in the TCG TLB.
* Using these should be a bit more self-documenting than using the
* generic target bits directly.
*/
#define arm_tlb_bti_gp(x) (typecheck_memtxattrs(x)->target_tlb_bit0)
/*
* Naming convention for isar_feature functions:
* Functions which test 32-bit ID registers should have _aa32_ in