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intel-iommu: update iq_dw during post load

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We need to update iq_dw according to the DMA_IRQ_REG during post
load. Otherwise we may get wrong IOTLB invalidation descriptor after
migration.

Fixes: fb43cf739e ("intel_iommu: scalable mode emulation")
Signed-off-by: Jason Wang <jasowang@redhat.com>
Message-Id: <20220317080522.14621-2-jasowang@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Peter Xu <peterx@redhat.com>
This commit is contained in:
Jason Wang 2022-03-17 16:05:22 +08:00 • committed by Michael S. Tsirkin
parent ceb058955a
commit 147a372e75
1 changed files with 15 additions and 6 deletions
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21
hw/i386/intel_iommu.c
View file

@ -181,6 +181,18 @@ static void vtd_update_scalable_state(IntelIOMMUState *s)
} }
} }
static void vtd_update_iq_dw(IntelIOMMUState *s)
{
uint64_t val = vtd_get_quad_raw(s, DMAR_IQA_REG);
if (s->ecap & VTD_ECAP_SMTS &&
val & VTD_IQA_DW_MASK) {
s->iq_dw = true;
} else {
s->iq_dw = false;
}
}
/* Whether the address space needs to notify new mappings */ /* Whether the address space needs to notify new mappings */
static inline gboolean vtd_as_has_map_notifier(VTDAddressSpace *as) static inline gboolean vtd_as_has_map_notifier(VTDAddressSpace *as)
{ {
@ -2904,12 +2916,7 @@ static void vtd_mem_write(void *opaque, hwaddr addr,
} else { } else {
vtd_set_quad(s, addr, val); vtd_set_quad(s, addr, val);
} }
if (s->ecap & VTD_ECAP_SMTS && vtd_update_iq_dw(s);
val & VTD_IQA_DW_MASK) {
s->iq_dw = true;
} else {
s->iq_dw = false;
}
break; break;
case DMAR_IQA_REG_HI: case DMAR_IQA_REG_HI:
@ -3082,6 +3089,8 @@ static int vtd_post_load(void *opaque, int version_id)
*/ */
vtd_update_scalable_state(iommu); vtd_update_scalable_state(iommu);
vtd_update_iq_dw(iommu);
/* /*
* Memory regions are dynamically turned on/off depending on * Memory regions are dynamically turned on/off depending on
* context entry configurations from the guest. After migration, * context entry configurations from the guest. After migration,