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tcg: TCGMemOp is now accelerator independent MemOp

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Preparation for collapsing the two byte swaps, adjust_endianness and
handle_bswap, along the I/O path.

Target dependant attributes are conditionalized upon NEED_CPU_H.

Signed-off-by: Tony Nguyen <tony.nguyen@bt.com>
Acked-by: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Acked-by: Cornelia Huck <cohuck@redhat.com>
Message-Id: <81d9cd7d7f5aaadfa772d6c48ecee834e9cf7882.1566466906.git.tony.nguyen@bt.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Tony Nguyen 2019-08-24 04:10:58 +10:00 • committed by Richard Henderson
parent fec105c2ab
commit 14776ab5a1
39 changed files with 418 additions and 396 deletions
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4
target/openrisc/translate.c
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@ -681,7 +681,7 @@ static bool trans_l_lwa(DisasContext *dc, arg_load *a)
return true;
}
static void do_load(DisasContext *dc, arg_load *a, TCGMemOp mop)
static void do_load(DisasContext *dc, arg_load *a, MemOp mop)
{
TCGv ea;
@ -763,7 +763,7 @@ static bool trans_l_swa(DisasContext *dc, arg_store *a)
return true;
}
static void do_store(DisasContext *dc, arg_store *a, TCGMemOp mop)
static void do_store(DisasContext *dc, arg_store *a, MemOp mop)
{
TCGv t0 = tcg_temp_new();
tcg_gen_addi_tl(t0, cpu_R[a->a], a->i);