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target/arm: Rename DISAS_UPDATE to DISAS_UPDATE_EXIT

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Emphasize that the is_jmp option exits to the main loop.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200626033144.790098-6-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson 2020-06-25 20:31:03 -07:00 • committed by Peter Maydell
parent 8ddb300bf6
commit 14407ec200
4 changed files with 20 additions and 18 deletions
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8
target/arm/translate-a64.c
View file

@ -1616,7 +1616,7 @@ static void handle_msr_i(DisasContext *s, uint32_t insn,
gen_helper_msr_i_daifclear(cpu_env, t1); gen_helper_msr_i_daifclear(cpu_env, t1);
tcg_temp_free_i32(t1); tcg_temp_free_i32(t1);
/* For DAIFClear, exit the cpu loop to re-evaluate pending IRQs. */ /* For DAIFClear, exit the cpu loop to re-evaluate pending IRQs. */
s->base.is_jmp = DISAS_UPDATE; s->base.is_jmp = DISAS_UPDATE_EXIT;
break; break;
default: default:
@ -1795,7 +1795,7 @@ static void handle_sys(DisasContext *s, uint32_t insn, bool isread,
if ((tb_cflags(s->base.tb) & CF_USE_ICOUNT) && (ri->type & ARM_CP_IO)) { if ((tb_cflags(s->base.tb) & CF_USE_ICOUNT) && (ri->type & ARM_CP_IO)) {
/* I/O operations must end the TB here (whether read or write) */ /* I/O operations must end the TB here (whether read or write) */
s->base.is_jmp = DISAS_UPDATE; s->base.is_jmp = DISAS_UPDATE_EXIT;
} }
if (!isread && !(ri->type & ARM_CP_SUPPRESS_TB_END)) { if (!isread && !(ri->type & ARM_CP_SUPPRESS_TB_END)) {
/* /*
@ -1810,7 +1810,7 @@ static void handle_sys(DisasContext *s, uint32_t insn, bool isread,
* but allow this to be suppressed by the register definition * but allow this to be suppressed by the register definition
* (usually only necessary to work around guest bugs). * (usually only necessary to work around guest bugs).
*/ */
s->base.is_jmp = DISAS_UPDATE; s->base.is_jmp = DISAS_UPDATE_EXIT;
} }
} }
@ -14292,7 +14292,7 @@ static void aarch64_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
gen_goto_tb(dc, 1, dc->base.pc_next); gen_goto_tb(dc, 1, dc->base.pc_next);
break; break;
default: default:
case DISAS_UPDATE: case DISAS_UPDATE_EXIT:
gen_a64_set_pc_im(dc->base.pc_next); gen_a64_set_pc_im(dc->base.pc_next);
/* fall through */ /* fall through */
case DISAS_EXIT: case DISAS_EXIT:

4
target/arm/translate-vfp.inc.c
View file

@ -123,7 +123,7 @@ static bool full_vfp_access_check(DisasContext *s, bool ignore_vfp_enabled)
* this to be the last insn in the TB). * this to be the last insn in the TB).
*/ */
if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) {
s->base.is_jmp = DISAS_UPDATE; s->base.is_jmp = DISAS_UPDATE_EXIT;
gen_io_start(); gen_io_start();
} }
gen_helper_v7m_preserve_fp_state(cpu_env); gen_helper_v7m_preserve_fp_state(cpu_env);
@ -2860,6 +2860,6 @@ static bool trans_VLLDM_VLSTM(DisasContext *s, arg_VLLDM_VLSTM *a)
tcg_temp_free_i32(fptr); tcg_temp_free_i32(fptr);
/* End the TB, because we have updated FP control bits */ /* End the TB, because we have updated FP control bits */
s->base.is_jmp = DISAS_UPDATE; s->base.is_jmp = DISAS_UPDATE_EXIT;
return true; return true;
} }

12
target/arm/translate.c
View file

@ -2775,7 +2775,7 @@ static void gen_msr_banked(DisasContext *s, int r, int sysm, int rn)
tcg_temp_free_i32(tcg_tgtmode); tcg_temp_free_i32(tcg_tgtmode);
tcg_temp_free_i32(tcg_regno); tcg_temp_free_i32(tcg_regno);
tcg_temp_free_i32(tcg_reg); tcg_temp_free_i32(tcg_reg);
s->base.is_jmp = DISAS_UPDATE; s->base.is_jmp = DISAS_UPDATE_EXIT;
} }
static void gen_mrs_banked(DisasContext *s, int r, int sysm, int rn) static void gen_mrs_banked(DisasContext *s, int r, int sysm, int rn)
@ -2797,7 +2797,7 @@ static void gen_mrs_banked(DisasContext *s, int r, int sysm, int rn)
tcg_temp_free_i32(tcg_tgtmode); tcg_temp_free_i32(tcg_tgtmode);
tcg_temp_free_i32(tcg_regno); tcg_temp_free_i32(tcg_regno);
store_reg(s, rn, tcg_reg); store_reg(s, rn, tcg_reg);
s->base.is_jmp = DISAS_UPDATE; s->base.is_jmp = DISAS_UPDATE_EXIT;
} }
/* Store value to PC as for an exception return (ie don't /* Store value to PC as for an exception return (ie don't
@ -5114,7 +5114,7 @@ static void gen_srs(DisasContext *s,
tcg_temp_free_i32(tmp); tcg_temp_free_i32(tmp);
} }
tcg_temp_free_i32(addr); tcg_temp_free_i32(addr);
s->base.is_jmp = DISAS_UPDATE; s->base.is_jmp = DISAS_UPDATE_EXIT;
} }
/* Generate a label used for skipping this instruction */ /* Generate a label used for skipping this instruction */
@ -8160,7 +8160,7 @@ static bool trans_SETEND(DisasContext *s, arg_SETEND *a)
} }
if (a->E != (s->be_data == MO_BE)) { if (a->E != (s->be_data == MO_BE)) {
gen_helper_setend(cpu_env); gen_helper_setend(cpu_env);
s->base.is_jmp = DISAS_UPDATE; s->base.is_jmp = DISAS_UPDATE_EXIT;
} }
return true; return true;
} }
@ -8873,7 +8873,7 @@ static void arm_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
break; break;
case DISAS_NEXT: case DISAS_NEXT:
case DISAS_TOO_MANY: case DISAS_TOO_MANY:
case DISAS_UPDATE: case DISAS_UPDATE_EXIT:
gen_set_pc_im(dc, dc->base.pc_next); gen_set_pc_im(dc, dc->base.pc_next);
/* fall through */ /* fall through */
default: default:
@ -8900,7 +8900,7 @@ static void arm_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
case DISAS_JUMP: case DISAS_JUMP:
gen_goto_ptr(); gen_goto_ptr();
break; break;
case DISAS_UPDATE: case DISAS_UPDATE_EXIT:
gen_set_pc_im(dc, dc->base.pc_next); gen_set_pc_im(dc, dc->base.pc_next);
/* fall through */ /* fall through */
default: default:

14
target/arm/translate.h
View file

@ -148,7 +148,8 @@ static inline void disas_set_insn_syndrome(DisasContext *s, uint32_t syn)
/* is_jmp field values */ /* is_jmp field values */
#define DISAS_JUMP DISAS_TARGET_0 /* only pc was modified dynamically */ #define DISAS_JUMP DISAS_TARGET_0 /* only pc was modified dynamically */
#define DISAS_UPDATE DISAS_TARGET_1 /* cpu state was modified dynamically */ /* CPU state was modified dynamically; exit to main loop for interrupts. */
#define DISAS_UPDATE_EXIT DISAS_TARGET_1
/* These instructions trap after executing, so the A32/T32 decoder must /* These instructions trap after executing, so the A32/T32 decoder must
* defer them until after the conditional execution state has been updated. * defer them until after the conditional execution state has been updated.
* WFI also needs special handling when single-stepping. * WFI also needs special handling when single-stepping.
@ -164,11 +165,12 @@ static inline void disas_set_insn_syndrome(DisasContext *s, uint32_t syn)
* custom end-of-TB code) * custom end-of-TB code)
*/ */
#define DISAS_BX_EXCRET DISAS_TARGET_8 #define DISAS_BX_EXCRET DISAS_TARGET_8
/* For instructions which want an immediate exit to the main loop, /*
* as opposed to attempting to use lookup_and_goto_ptr. Unlike * For instructions which want an immediate exit to the main loop, as opposed
* DISAS_UPDATE this doesn't write the PC on exiting the translation * to attempting to use lookup_and_goto_ptr. Unlike DISAS_UPDATE_EXIT, this
* loop so you need to ensure something (gen_a64_set_pc_im or runtime * doesn't write the PC on exiting the translation loop so you need to ensure
* helper) has done so before we reach return from cpu_tb_exec. * something (gen_a64_set_pc_im or runtime helper) has done so before we reach
* return from cpu_tb_exec.
*/ */
#define DISAS_EXIT DISAS_TARGET_9 #define DISAS_EXIT DISAS_TARGET_9