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hw/misc/stm32l4x5_rcc: Initialize PLLs and clock multiplexers
Instantiate the whole clock tree and using the Clock multiplexers and the PLLs defined in the previous commits. This allows to statically define the clock tree and easily follow the clock signal from one end to another. Also handle three-phase reset now that we have defined a known base state for every object. (Reset handling based on hw/misc/zynq_sclr.c) Signed-off-by: Arnaud Minier <arnaud.minier@telecom-paris.fr> Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr> Message-id: 20240303140643.81957-5-arnaud.minier@telecom-paris.fr Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Arnaud Minier
Peter Maydell
parent
6487653efd
commit
141c29a23b
2 changed files with 833 additions and 17 deletions
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@ -334,4 +334,709 @@ typedef enum RccClockMuxSource {
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RCC_CLOCK_MUX_SRC_NUMBER,
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} RccClockMuxSource;
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/* PLL init info */
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typedef struct PllInitInfo {
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const char *name;
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const char *channel_name[RCC_NUM_CHANNEL_PLL_OUT];
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bool channel_exists[RCC_NUM_CHANNEL_PLL_OUT];
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uint32_t default_channel_divider[RCC_NUM_CHANNEL_PLL_OUT];
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RccClockMuxSource src_mapping[RCC_NUM_CLOCK_MUX_SRC];
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} PllInitInfo;
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static const PllInitInfo PLL_INIT_INFO[] = {
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[RCC_PLL_PLL] = {
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.name = "pll",
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.channel_name = {
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"pllsai3clk",
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"pll48m1clk",
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"pllclk"
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},
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.channel_exists = {
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true, true, true
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},
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/* From PLLCFGR register documentation */
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.default_channel_divider = {
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7, 2, 2
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}
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},
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[RCC_PLL_PLLSAI1] = {
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.name = "pllsai1",
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.channel_name = {
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"pllsai1clk",
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"pll48m2clk",
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"plladc1clk"
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},
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.channel_exists = {
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true, true, true
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},
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/* From PLLSAI1CFGR register documentation */
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.default_channel_divider = {
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7, 2, 2
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}
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},
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[RCC_PLL_PLLSAI2] = {
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.name = "pllsai2",
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.channel_name = {
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"pllsai2clk",
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NULL,
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"plladc2clk"
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},
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.channel_exists = {
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true, false, true
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},
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/* From PLLSAI2CFGR register documentation */
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.default_channel_divider = {
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7, 0, 2
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}
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}
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};
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static inline void set_pll_init_info(RccPllState *pll,
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RccPll id)
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{
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int i;
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pll->id = id;
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pll->vco_multiplier = 1;
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for (i = 0; i < RCC_NUM_CHANNEL_PLL_OUT; i++) {
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pll->channel_enabled[i] = false;
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pll->channel_exists[i] = PLL_INIT_INFO[id].channel_exists[i];
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pll->channel_divider[i] = PLL_INIT_INFO[id].default_channel_divider[i];
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}
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}
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/* Clock mux init info */
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typedef struct ClockMuxInitInfo {
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const char *name;
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uint32_t multiplier;
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uint32_t divider;
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bool enabled;
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/* If this is true, the clock will not be exposed outside of the device */
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bool hidden;
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RccClockMuxSource src_mapping[RCC_NUM_CLOCK_MUX_SRC];
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} ClockMuxInitInfo;
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#define FILL_DEFAULT_FACTOR \
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.multiplier = 1, \
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.divider = 1
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#define FILL_DEFAULT_INIT_ENABLED \
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FILL_DEFAULT_FACTOR, \
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.enabled = true
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#define FILL_DEFAULT_INIT_DISABLED \
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FILL_DEFAULT_FACTOR, \
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.enabled = false
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static const ClockMuxInitInfo CLOCK_MUX_INIT_INFO[] = {
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[RCC_CLOCK_MUX_SYSCLK] = {
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.name = "sysclk",
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/* Same mapping as: CFGR_SW */
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.src_mapping = {
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RCC_CLOCK_MUX_SRC_MSI,
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RCC_CLOCK_MUX_SRC_HSI,
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RCC_CLOCK_MUX_SRC_HSE,
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RCC_CLOCK_MUX_SRC_PLL,
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},
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.hidden = true,
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FILL_DEFAULT_INIT_ENABLED,
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},
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[RCC_CLOCK_MUX_PLL_INPUT] = {
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.name = "pll-input",
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/* Same mapping as: PLLCFGR_PLLSRC */
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.src_mapping = {
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RCC_CLOCK_MUX_SRC_MSI,
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RCC_CLOCK_MUX_SRC_HSI,
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RCC_CLOCK_MUX_SRC_HSE,
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},
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.hidden = true,
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FILL_DEFAULT_INIT_ENABLED,
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},
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[RCC_CLOCK_MUX_HCLK] = {
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.name = "hclk",
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.src_mapping = {
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RCC_CLOCK_MUX_SRC_SYSCLK,
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},
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.hidden = true,
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FILL_DEFAULT_INIT_ENABLED,
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},
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[RCC_CLOCK_MUX_PCLK1] = {
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.name = "pclk1",
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.src_mapping = {
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RCC_CLOCK_MUX_SRC_HCLK,
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},
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.hidden = true,
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FILL_DEFAULT_INIT_ENABLED,
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},
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[RCC_CLOCK_MUX_PCLK2] = {
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.name = "pclk2",
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.src_mapping = {
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RCC_CLOCK_MUX_SRC_HCLK,
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},
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.hidden = true,
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FILL_DEFAULT_INIT_ENABLED,
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},
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[RCC_CLOCK_MUX_HSE_OVER_32] = {
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.name = "hse-divided-by-32",
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.multiplier = 1,
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.divider = 32,
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.enabled = true,
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.src_mapping = {
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RCC_CLOCK_MUX_SRC_HSE,
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},
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.hidden = true,
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},
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[RCC_CLOCK_MUX_LCD_AND_RTC_COMMON] = {
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.name = "lcd-and-rtc-common-mux",
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/* Same mapping as: BDCR_RTCSEL */
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.src_mapping = {
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RCC_CLOCK_MUX_SRC_GND,
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RCC_CLOCK_MUX_SRC_LSE,
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RCC_CLOCK_MUX_SRC_LSI,
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RCC_CLOCK_MUX_SRC_HSE_OVER_32,
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},
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.hidden = true,
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FILL_DEFAULT_INIT_ENABLED,
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},
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/* From now on, muxes with a publicly available output */
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[RCC_CLOCK_MUX_CORTEX_REFCLK] = {
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.name = "cortex-refclk",
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.multiplier = 1,
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/* REFCLK is always HCLK/8 */
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.divider = 8,
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.enabled = true,
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.src_mapping = {
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RCC_CLOCK_MUX_SRC_HCLK,
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}
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},
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[RCC_CLOCK_MUX_USART1] = {
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.name = "usart1",
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/* Same mapping as: CCIPR_USART1SEL */
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.src_mapping = {
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RCC_CLOCK_MUX_SRC_PCLK2,
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RCC_CLOCK_MUX_SRC_SYSCLK,
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RCC_CLOCK_MUX_SRC_HSI,
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RCC_CLOCK_MUX_SRC_LSE,
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},
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FILL_DEFAULT_INIT_DISABLED,
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},
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[RCC_CLOCK_MUX_USART2] = {
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.name = "usart2",
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/* Same mapping as: CCIPR_USART2SEL */
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.src_mapping = {
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RCC_CLOCK_MUX_SRC_PCLK1,
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RCC_CLOCK_MUX_SRC_SYSCLK,
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RCC_CLOCK_MUX_SRC_HSI,
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RCC_CLOCK_MUX_SRC_LSE,
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},
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FILL_DEFAULT_INIT_DISABLED,
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},
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[RCC_CLOCK_MUX_USART3] = {
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.name = "usart3",
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/* Same mapping as: CCIPR_USART3SEL */
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.src_mapping = {
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RCC_CLOCK_MUX_SRC_PCLK1,
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RCC_CLOCK_MUX_SRC_SYSCLK,
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RCC_CLOCK_MUX_SRC_HSI,
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RCC_CLOCK_MUX_SRC_LSE,
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},
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FILL_DEFAULT_INIT_DISABLED,
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},
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[RCC_CLOCK_MUX_UART4] = {
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.name = "uart4",
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/* Same mapping as: CCIPR_UART4SEL */
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.src_mapping = {
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RCC_CLOCK_MUX_SRC_PCLK1,
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RCC_CLOCK_MUX_SRC_SYSCLK,
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RCC_CLOCK_MUX_SRC_HSI,
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RCC_CLOCK_MUX_SRC_LSE,
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},
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FILL_DEFAULT_INIT_DISABLED,
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},
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[RCC_CLOCK_MUX_UART5] = {
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.name = "uart5",
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/* Same mapping as: CCIPR_UART5SEL */
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.src_mapping = {
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RCC_CLOCK_MUX_SRC_PCLK1,
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RCC_CLOCK_MUX_SRC_SYSCLK,
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RCC_CLOCK_MUX_SRC_HSI,
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RCC_CLOCK_MUX_SRC_LSE,
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},
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FILL_DEFAULT_INIT_DISABLED,
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},
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[RCC_CLOCK_MUX_LPUART1] = {
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.name = "lpuart1",
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/* Same mapping as: CCIPR_LPUART1SEL */
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.src_mapping = {
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RCC_CLOCK_MUX_SRC_PCLK1,
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RCC_CLOCK_MUX_SRC_SYSCLK,
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RCC_CLOCK_MUX_SRC_HSI,
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RCC_CLOCK_MUX_SRC_LSE,
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},
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FILL_DEFAULT_INIT_DISABLED,
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},
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[RCC_CLOCK_MUX_I2C1] = {
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.name = "i2c1",
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/* Same mapping as: CCIPR_I2C1SEL */
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.src_mapping = {
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RCC_CLOCK_MUX_SRC_PCLK1,
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RCC_CLOCK_MUX_SRC_SYSCLK,
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RCC_CLOCK_MUX_SRC_HSI,
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},
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FILL_DEFAULT_INIT_DISABLED,
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},
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[RCC_CLOCK_MUX_I2C2] = {
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.name = "i2c2",
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/* Same mapping as: CCIPR_I2C2SEL */
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.src_mapping = {
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RCC_CLOCK_MUX_SRC_PCLK1,
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RCC_CLOCK_MUX_SRC_SYSCLK,
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RCC_CLOCK_MUX_SRC_HSI,
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},
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FILL_DEFAULT_INIT_DISABLED,
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},
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[RCC_CLOCK_MUX_I2C3] = {
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.name = "i2c3",
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/* Same mapping as: CCIPR_I2C3SEL */
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.src_mapping = {
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RCC_CLOCK_MUX_SRC_PCLK1,
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RCC_CLOCK_MUX_SRC_SYSCLK,
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RCC_CLOCK_MUX_SRC_HSI,
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},
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FILL_DEFAULT_INIT_DISABLED,
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},
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[RCC_CLOCK_MUX_LPTIM1] = {
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.name = "lptim1",
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/* Same mapping as: CCIPR_LPTIM1SEL */
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.src_mapping = {
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RCC_CLOCK_MUX_SRC_PCLK1,
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RCC_CLOCK_MUX_SRC_LSI,
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RCC_CLOCK_MUX_SRC_HSI,
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RCC_CLOCK_MUX_SRC_LSE,
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},
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FILL_DEFAULT_INIT_DISABLED,
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},
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[RCC_CLOCK_MUX_LPTIM2] = {
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.name = "lptim2",
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/* Same mapping as: CCIPR_LPTIM2SEL */
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.src_mapping = {
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RCC_CLOCK_MUX_SRC_PCLK1,
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RCC_CLOCK_MUX_SRC_LSI,
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RCC_CLOCK_MUX_SRC_HSI,
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RCC_CLOCK_MUX_SRC_LSE,
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},
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FILL_DEFAULT_INIT_DISABLED,
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},
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[RCC_CLOCK_MUX_SWPMI1] = {
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.name = "swpmi1",
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/* Same mapping as: CCIPR_SWPMI1SEL */
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.src_mapping = {
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RCC_CLOCK_MUX_SRC_PCLK1,
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RCC_CLOCK_MUX_SRC_HSI,
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},
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FILL_DEFAULT_INIT_DISABLED,
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},
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[RCC_CLOCK_MUX_MCO] = {
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.name = "mco",
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/* Same mapping as: CFGR_MCOSEL */
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.src_mapping = {
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RCC_CLOCK_MUX_SRC_SYSCLK,
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RCC_CLOCK_MUX_SRC_MSI,
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RCC_CLOCK_MUX_SRC_HSI,
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RCC_CLOCK_MUX_SRC_HSE,
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RCC_CLOCK_MUX_SRC_PLL,
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RCC_CLOCK_MUX_SRC_LSI,
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RCC_CLOCK_MUX_SRC_LSE,
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},
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FILL_DEFAULT_INIT_DISABLED,
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},
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[RCC_CLOCK_MUX_LSCO] = {
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.name = "lsco",
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/* Same mapping as: BDCR_LSCOSEL */
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.src_mapping = {
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RCC_CLOCK_MUX_SRC_LSI,
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RCC_CLOCK_MUX_SRC_LSE,
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},
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FILL_DEFAULT_INIT_DISABLED,
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},
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[RCC_CLOCK_MUX_DFSDM1] = {
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.name = "dfsdm1",
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/* Same mapping as: CCIPR_DFSDM1SEL */
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.src_mapping = {
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RCC_CLOCK_MUX_SRC_PCLK2,
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RCC_CLOCK_MUX_SRC_SYSCLK,
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},
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FILL_DEFAULT_INIT_DISABLED,
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},
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[RCC_CLOCK_MUX_ADC] = {
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.name = "adc",
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/* Same mapping as: CCIPR_ADCSEL */
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.src_mapping = {
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RCC_CLOCK_MUX_SRC_GND,
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RCC_CLOCK_MUX_SRC_PLLADC1,
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RCC_CLOCK_MUX_SRC_PLLADC2,
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RCC_CLOCK_MUX_SRC_SYSCLK,
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},
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FILL_DEFAULT_INIT_DISABLED,
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},
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[RCC_CLOCK_MUX_CLK48] = {
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.name = "clk48",
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/* Same mapping as: CCIPR_CLK48SEL */
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.src_mapping = {
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RCC_CLOCK_MUX_SRC_GND,
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RCC_CLOCK_MUX_SRC_PLL48M2,
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RCC_CLOCK_MUX_SRC_PLL48M1,
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RCC_CLOCK_MUX_SRC_MSI,
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},
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FILL_DEFAULT_INIT_DISABLED,
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},
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[RCC_CLOCK_MUX_SAI2] = {
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.name = "sai2",
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/* Same mapping as: CCIPR_SAI2SEL */
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.src_mapping = {
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RCC_CLOCK_MUX_SRC_PLLSAI1,
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RCC_CLOCK_MUX_SRC_PLLSAI2,
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RCC_CLOCK_MUX_SRC_PLLSAI3,
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RCC_CLOCK_MUX_SRC_SAI2_EXTCLK,
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},
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FILL_DEFAULT_INIT_DISABLED,
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},
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[RCC_CLOCK_MUX_SAI1] = {
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.name = "sai1",
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/* Same mapping as: CCIPR_SAI1SEL */
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.src_mapping = {
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RCC_CLOCK_MUX_SRC_PLLSAI1,
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RCC_CLOCK_MUX_SRC_PLLSAI2,
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RCC_CLOCK_MUX_SRC_PLLSAI3,
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RCC_CLOCK_MUX_SRC_SAI1_EXTCLK,
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},
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FILL_DEFAULT_INIT_DISABLED,
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},
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/* From now on, these muxes only have one valid source */
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[RCC_CLOCK_MUX_TSC] = {
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.name = "tsc",
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.src_mapping = {
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RCC_CLOCK_MUX_SRC_SYSCLK,
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},
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FILL_DEFAULT_INIT_DISABLED,
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},
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[RCC_CLOCK_MUX_CRC] = {
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.name = "crc",
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.src_mapping = {
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RCC_CLOCK_MUX_SRC_SYSCLK,
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},
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FILL_DEFAULT_INIT_DISABLED,
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},
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[RCC_CLOCK_MUX_FLASH] = {
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.name = "flash",
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.src_mapping = {
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RCC_CLOCK_MUX_SRC_SYSCLK,
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},
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FILL_DEFAULT_INIT_DISABLED,
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},
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[RCC_CLOCK_MUX_DMA2] = {
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.name = "dma2",
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.src_mapping = {
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RCC_CLOCK_MUX_SRC_SYSCLK,
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},
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FILL_DEFAULT_INIT_DISABLED,
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},
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[RCC_CLOCK_MUX_DMA1] = {
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.name = "dma1",
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.src_mapping = {
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RCC_CLOCK_MUX_SRC_SYSCLK,
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},
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FILL_DEFAULT_INIT_DISABLED,
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},
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[RCC_CLOCK_MUX_RNG] = {
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.name = "rng",
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.src_mapping = {
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RCC_CLOCK_MUX_SRC_SYSCLK,
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},
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FILL_DEFAULT_INIT_DISABLED,
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},
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[RCC_CLOCK_MUX_AES] = {
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.name = "aes",
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.src_mapping = {
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RCC_CLOCK_MUX_SRC_SYSCLK,
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},
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FILL_DEFAULT_INIT_DISABLED,
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},
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[RCC_CLOCK_MUX_OTGFS] = {
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.name = "otgfs",
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.src_mapping = {
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RCC_CLOCK_MUX_SRC_SYSCLK,
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},
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FILL_DEFAULT_INIT_DISABLED,
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},
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[RCC_CLOCK_MUX_GPIOA] = {
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.name = "gpioa",
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.src_mapping = {
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RCC_CLOCK_MUX_SRC_SYSCLK,
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},
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FILL_DEFAULT_INIT_DISABLED,
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},
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[RCC_CLOCK_MUX_GPIOB] = {
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.name = "gpiob",
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.src_mapping = {
|
||||
RCC_CLOCK_MUX_SRC_SYSCLK,
|
||||
},
|
||||
FILL_DEFAULT_INIT_DISABLED,
|
||||
},
|
||||
[RCC_CLOCK_MUX_GPIOC] = {
|
||||
.name = "gpioc",
|
||||
.src_mapping = {
|
||||
RCC_CLOCK_MUX_SRC_SYSCLK,
|
||||
},
|
||||
FILL_DEFAULT_INIT_DISABLED,
|
||||
},
|
||||
[RCC_CLOCK_MUX_GPIOD] = {
|
||||
.name = "gpiod",
|
||||
.src_mapping = {
|
||||
RCC_CLOCK_MUX_SRC_SYSCLK,
|
||||
},
|
||||
FILL_DEFAULT_INIT_DISABLED,
|
||||
},
|
||||
[RCC_CLOCK_MUX_GPIOE] = {
|
||||
.name = "gpioe",
|
||||
.src_mapping = {
|
||||
RCC_CLOCK_MUX_SRC_SYSCLK,
|
||||
},
|
||||
FILL_DEFAULT_INIT_DISABLED,
|
||||
},
|
||||
[RCC_CLOCK_MUX_GPIOF] = {
|
||||
.name = "gpiof",
|
||||
.src_mapping = {
|
||||
RCC_CLOCK_MUX_SRC_SYSCLK,
|
||||
},
|
||||
FILL_DEFAULT_INIT_DISABLED,
|
||||
},
|
||||
[RCC_CLOCK_MUX_GPIOG] = {
|
||||
.name = "gpiog",
|
||||
.src_mapping = {
|
||||
RCC_CLOCK_MUX_SRC_SYSCLK,
|
||||
},
|
||||
FILL_DEFAULT_INIT_DISABLED,
|
||||
},
|
||||
[RCC_CLOCK_MUX_GPIOH] = {
|
||||
.name = "gpioh",
|
||||
.src_mapping = {
|
||||
RCC_CLOCK_MUX_SRC_SYSCLK,
|
||||
},
|
||||
FILL_DEFAULT_INIT_DISABLED,
|
||||
},
|
||||
[RCC_CLOCK_MUX_QSPI] = {
|
||||
.name = "qspi",
|
||||
.src_mapping = {
|
||||
RCC_CLOCK_MUX_SRC_SYSCLK,
|
||||
},
|
||||
FILL_DEFAULT_INIT_DISABLED,
|
||||
},
|
||||
[RCC_CLOCK_MUX_FMC] = {
|
||||
.name = "fmc",
|
||||
.src_mapping = {
|
||||
RCC_CLOCK_MUX_SRC_SYSCLK,
|
||||
},
|
||||
FILL_DEFAULT_INIT_DISABLED,
|
||||
},
|
||||
[RCC_CLOCK_MUX_OPAMP] = {
|
||||
.name = "opamp",
|
||||
.src_mapping = {
|
||||
RCC_CLOCK_MUX_SRC_PCLK1,
|
||||
},
|
||||
FILL_DEFAULT_INIT_DISABLED,
|
||||
},
|
||||
[RCC_CLOCK_MUX_DAC1] = {
|
||||
.name = "dac1",
|
||||
.src_mapping = {
|
||||
RCC_CLOCK_MUX_SRC_PCLK1,
|
||||
},
|
||||
FILL_DEFAULT_INIT_DISABLED,
|
||||
},
|
||||
[RCC_CLOCK_MUX_PWR] = {
|
||||
.name = "pwr",
|
||||
/*
|
||||
* PWREN is in the APB1ENR1 register,
|
||||
* but PWR uses SYSCLK according to the clock tree.
|
||||
*/
|
||||
.src_mapping = {
|
||||
RCC_CLOCK_MUX_SRC_SYSCLK,
|
||||
},
|
||||
FILL_DEFAULT_INIT_DISABLED,
|
||||
},
|
||||
[RCC_CLOCK_MUX_CAN1] = {
|
||||
.name = "can1",
|
||||
.src_mapping = {
|
||||
RCC_CLOCK_MUX_SRC_PCLK1,
|
||||
},
|
||||
FILL_DEFAULT_INIT_DISABLED,
|
||||
},
|
||||
[RCC_CLOCK_MUX_SPI3] = {
|
||||
.name = "spi3",
|
||||
.src_mapping = {
|
||||
RCC_CLOCK_MUX_SRC_PCLK1,
|
||||
},
|
||||
FILL_DEFAULT_INIT_DISABLED,
|
||||
},
|
||||
[RCC_CLOCK_MUX_SPI2] = {
|
||||
.name = "spi2",
|
||||
.src_mapping = {
|
||||
RCC_CLOCK_MUX_SRC_PCLK1,
|
||||
},
|
||||
FILL_DEFAULT_INIT_DISABLED,
|
||||
},
|
||||
[RCC_CLOCK_MUX_WWDG] = {
|
||||
.name = "wwdg",
|
||||
.src_mapping = {
|
||||
RCC_CLOCK_MUX_SRC_PCLK1,
|
||||
},
|
||||
FILL_DEFAULT_INIT_DISABLED,
|
||||
},
|
||||
[RCC_CLOCK_MUX_LCD] = {
|
||||
.name = "lcd",
|
||||
.src_mapping = {
|
||||
RCC_CLOCK_MUX_SRC_LCD_AND_RTC_COMMON,
|
||||
},
|
||||
FILL_DEFAULT_INIT_DISABLED,
|
||||
},
|
||||
[RCC_CLOCK_MUX_TIM7] = {
|
||||
.name = "tim7",
|
||||
.src_mapping = {
|
||||
RCC_CLOCK_MUX_SRC_PCLK1,
|
||||
},
|
||||
FILL_DEFAULT_INIT_DISABLED,
|
||||
},
|
||||
[RCC_CLOCK_MUX_TIM6] = {
|
||||
.name = "tim6",
|
||||
.src_mapping = {
|
||||
RCC_CLOCK_MUX_SRC_PCLK1,
|
||||
},
|
||||
FILL_DEFAULT_INIT_DISABLED,
|
||||
},
|
||||
[RCC_CLOCK_MUX_TIM5] = {
|
||||
.name = "tim5",
|
||||
.src_mapping = {
|
||||
RCC_CLOCK_MUX_SRC_PCLK1,
|
||||
},
|
||||
FILL_DEFAULT_INIT_DISABLED,
|
||||
},
|
||||
[RCC_CLOCK_MUX_TIM4] = {
|
||||
.name = "tim4",
|
||||
.src_mapping = {
|
||||
RCC_CLOCK_MUX_SRC_PCLK1,
|
||||
},
|
||||
FILL_DEFAULT_INIT_DISABLED,
|
||||
},
|
||||
[RCC_CLOCK_MUX_TIM3] = {
|
||||
.name = "tim3",
|
||||
.src_mapping = {
|
||||
RCC_CLOCK_MUX_SRC_PCLK1,
|
||||
},
|
||||
FILL_DEFAULT_INIT_DISABLED,
|
||||
},
|
||||
[RCC_CLOCK_MUX_TIM2] = {
|
||||
.name = "tim2",
|
||||
.src_mapping = {
|
||||
RCC_CLOCK_MUX_SRC_PCLK1,
|
||||
},
|
||||
FILL_DEFAULT_INIT_DISABLED,
|
||||
},
|
||||
[RCC_CLOCK_MUX_TIM17] = {
|
||||
.name = "tim17",
|
||||
.src_mapping = {
|
||||
RCC_CLOCK_MUX_SRC_PCLK2,
|
||||
},
|
||||
FILL_DEFAULT_INIT_DISABLED,
|
||||
},
|
||||
[RCC_CLOCK_MUX_TIM16] = {
|
||||
.name = "tim16",
|
||||
.src_mapping = {
|
||||
RCC_CLOCK_MUX_SRC_PCLK2,
|
||||
},
|
||||
FILL_DEFAULT_INIT_DISABLED,
|
||||
},
|
||||
[RCC_CLOCK_MUX_TIM15] = {
|
||||
.name = "tim15",
|
||||
.src_mapping = {
|
||||
RCC_CLOCK_MUX_SRC_PCLK2,
|
||||
},
|
||||
FILL_DEFAULT_INIT_DISABLED,
|
||||
},
|
||||
[RCC_CLOCK_MUX_TIM8] = {
|
||||
.name = "tim8",
|
||||
.src_mapping = {
|
||||
RCC_CLOCK_MUX_SRC_PCLK2,
|
||||
},
|
||||
FILL_DEFAULT_INIT_DISABLED,
|
||||
},
|
||||
[RCC_CLOCK_MUX_SPI1] = {
|
||||
.name = "spi1",
|
||||
.src_mapping = {
|
||||
RCC_CLOCK_MUX_SRC_PCLK2,
|
||||
},
|
||||
FILL_DEFAULT_INIT_DISABLED,
|
||||
},
|
||||
[RCC_CLOCK_MUX_TIM1] = {
|
||||
.name = "tim1",
|
||||
.src_mapping = {
|
||||
RCC_CLOCK_MUX_SRC_PCLK2,
|
||||
},
|
||||
FILL_DEFAULT_INIT_DISABLED,
|
||||
},
|
||||
[RCC_CLOCK_MUX_SDMMC1] = {
|
||||
.name = "sdmmc1",
|
||||
.src_mapping = {
|
||||
RCC_CLOCK_MUX_SRC_PCLK2,
|
||||
},
|
||||
FILL_DEFAULT_INIT_DISABLED,
|
||||
},
|
||||
[RCC_CLOCK_MUX_FW] = {
|
||||
.name = "fw",
|
||||
.src_mapping = {
|
||||
RCC_CLOCK_MUX_SRC_PCLK2,
|
||||
},
|
||||
FILL_DEFAULT_INIT_DISABLED,
|
||||
},
|
||||
[RCC_CLOCK_MUX_SYSCFG] = {
|
||||
.name = "syscfg",
|
||||
.src_mapping = {
|
||||
RCC_CLOCK_MUX_SRC_PCLK2,
|
||||
},
|
||||
FILL_DEFAULT_INIT_DISABLED,
|
||||
},
|
||||
[RCC_CLOCK_MUX_RTC] = {
|
||||
.name = "rtc",
|
||||
.src_mapping = {
|
||||
RCC_CLOCK_MUX_SRC_LCD_AND_RTC_COMMON,
|
||||
},
|
||||
FILL_DEFAULT_INIT_DISABLED,
|
||||
},
|
||||
[RCC_CLOCK_MUX_CORTEX_FCLK] = {
|
||||
.name = "cortex-fclk",
|
||||
.src_mapping = {
|
||||
RCC_CLOCK_MUX_SRC_HCLK,
|
||||
},
|
||||
FILL_DEFAULT_INIT_ENABLED,
|
||||
},
|
||||
};
|
||||
|
||||
static inline void set_clock_mux_init_info(RccClockMuxState *mux,
|
||||
RccClockMux id)
|
||||
{
|
||||
mux->id = id;
|
||||
mux->multiplier = CLOCK_MUX_INIT_INFO[id].multiplier;
|
||||
mux->divider = CLOCK_MUX_INIT_INFO[id].divider;
|
||||
mux->enabled = CLOCK_MUX_INIT_INFO[id].enabled;
|
||||
/*
|
||||
* Every peripheral has the first source of their source list as
|
||||
* as their default source.
|
||||
*/
|
||||
mux->src = 0;
|
||||
}
|
||||
|
||||
#endif /* HW_STM32L4X5_RCC_INTERNALS_H */
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue