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q800-updates-for-7.0 queue
-----BEGIN PGP SIGNATURE----- iQFSBAABCgA8FiEEzGIauY6CIA2RXMnEW8LFb64PMh8FAmIoiAMeHG1hcmsuY2F2 ZS1heWxhbmRAaWxhbmRlLmNvLnVrAAoJEFvCxW+uDzIfcn0H+wfeA9uKZ9DNc20O XDkq2lnUiEyrKsZrVn8jRlw/zHnuElX2WmMGckisJpcaBpZSwlypHBhrjssUXu7v nHlrOYqoKxiYFSZVPj1n+P849BW3LKNgcA5/njA87QUjMOCW6eq4Sp9beDsSbw57 cPAXUhGNI4uvLh6ew9aoxz01KhBSY1hFMmX0U6gcDx48f5cr/NU81+Vae0+Ks3B+ BPbYjED3yr7G6nu63MT63WXlAnKBQpndkjbVYubQCwVJqLRBb6p37Gm81KXozpos QxF9miWdzA2dRCrSutcAd84rTWq2w8T2Wf2sW3B8lXNy+s+qTSnvsiOUjoaESzv7 UKXmYZE= =RwkZ -----END PGP SIGNATURE----- Merge remote-tracking branch 'remotes/mcayland/tags/q800-updates-for-7.0-20220309' into staging q800-updates-for-7.0 queue # gpg: Signature made Wed 09 Mar 2022 10:57:07 GMT # gpg: using RSA key CC621AB98E82200D915CC9C45BC2C56FAE0F321F # gpg: issuer "mark.cave-ayland@ilande.co.uk" # gpg: Good signature from "Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>" [full] # Primary key fingerprint: CC62 1AB9 8E82 200D 915C C9C4 5BC2 C56F AE0F 321F * remotes/mcayland/tags/q800-updates-for-7.0-20220309: (22 commits) esp: recreate ESPState current_req after migration esp: include the current PDMA callback in the migration stream esp: convert ESPState pdma_cb from a function pointer to an integer esp: introduce esp_pdma_cb() function esp: introduce esp_set_pdma_cb() function macfb: set initial value of mode control registers in macfb_common_realize() macfb: add VMStateDescription fields for display type and VBL timer macfb: increase number of registers saved in MacfbState macfb: don't use special irq_state and irq_mask variables in MacfbState macfb: add VMStateDescription for MacfbNubusState and MacfbSysBusState macio/pmu.c: remove redundant code mos6522: implement edge-triggering for CA1/2 and CB1/2 control line IRQs mac_via: make SCSI_DATA (DRQ) bit live rather than latched mos6522: record last_irq_levels in mos6522_set_irq() mos6522: add "info via" HMP command for debugging mos6522: add register names to register read/write trace events mos6522: use device_class_set_parent_reset() to propagate reset to parent mos6522: remove update_irq() and set_sr_int() methods from MOS6522DeviceClass mos6522: switch over to use qdev gpios for IRQs mac_via: use IFR bit flag constants for VIA2 IRQs ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell
commit
1416688c53
15 changed files with 473 additions and 169 deletions
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@ -48,7 +48,8 @@ typedef struct MacFbMode {
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uint32_t offset;
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} MacFbMode;
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#define MACFB_NUM_REGS 8
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#define MACFB_CTRL_TOPADDR 0x200
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#define MACFB_NUM_REGS (MACFB_CTRL_TOPADDR / sizeof(uint32_t))
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typedef struct MacfbState {
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MemoryRegion mem_vram;
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@ -66,8 +67,6 @@ typedef struct MacfbState {
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uint32_t regs[MACFB_NUM_REGS];
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MacFbMode *mode;
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uint32_t irq_state;
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uint32_t irq_mask;
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QEMUTimer *vbl_timer;
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qemu_irq irq;
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} MacfbState;
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@ -18,19 +18,17 @@
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#define VIA_SIZE 0x2000
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/* VIA 1 */
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#define VIA1_IRQ_ONE_SECOND_BIT 0
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#define VIA1_IRQ_60HZ_BIT 1
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#define VIA1_IRQ_ADB_READY_BIT 2
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#define VIA1_IRQ_ADB_DATA_BIT 3
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#define VIA1_IRQ_ADB_CLOCK_BIT 4
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#define VIA1_IRQ_ONE_SECOND_BIT CA2_INT_BIT
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#define VIA1_IRQ_60HZ_BIT CA1_INT_BIT
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#define VIA1_IRQ_ADB_READY_BIT SR_INT_BIT
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#define VIA1_IRQ_ADB_DATA_BIT CB2_INT_BIT
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#define VIA1_IRQ_ADB_CLOCK_BIT CB1_INT_BIT
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#define VIA1_IRQ_NB 8
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#define VIA1_IRQ_ONE_SECOND (1 << VIA1_IRQ_ONE_SECOND_BIT)
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#define VIA1_IRQ_60HZ (1 << VIA1_IRQ_60HZ_BIT)
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#define VIA1_IRQ_ADB_READY (1 << VIA1_IRQ_ADB_READY_BIT)
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#define VIA1_IRQ_ADB_DATA (1 << VIA1_IRQ_ADB_DATA_BIT)
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#define VIA1_IRQ_ADB_CLOCK (1 << VIA1_IRQ_ADB_CLOCK_BIT)
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#define VIA1_IRQ_ONE_SECOND BIT(VIA1_IRQ_ONE_SECOND_BIT)
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#define VIA1_IRQ_60HZ BIT(VIA1_IRQ_60HZ_BIT)
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#define VIA1_IRQ_ADB_READY BIT(VIA1_IRQ_ADB_READY_BIT)
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#define VIA1_IRQ_ADB_DATA BIT(VIA1_IRQ_ADB_DATA_BIT)
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#define VIA1_IRQ_ADB_CLOCK BIT(VIA1_IRQ_ADB_CLOCK_BIT)
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#define TYPE_MOS6522_Q800_VIA1 "mos6522-q800-via1"
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@ -42,7 +40,6 @@ struct MOS6522Q800VIA1State {
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MemoryRegion via_mem;
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qemu_irq irqs[VIA1_IRQ_NB];
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qemu_irq auxmode_irq;
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uint8_t last_b;
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@ -80,19 +77,16 @@ struct MOS6522Q800VIA1State {
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/* VIA 2 */
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#define VIA2_IRQ_SCSI_DATA_BIT 0
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#define VIA2_IRQ_NUBUS_BIT 1
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#define VIA2_IRQ_UNUSED_BIT 2
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#define VIA2_IRQ_SCSI_BIT 3
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#define VIA2_IRQ_ASC_BIT 4
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#define VIA2_IRQ_SCSI_DATA_BIT CA2_INT_BIT
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#define VIA2_IRQ_NUBUS_BIT CA1_INT_BIT
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#define VIA2_IRQ_SCSI_BIT CB2_INT_BIT
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#define VIA2_IRQ_ASC_BIT CB1_INT_BIT
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#define VIA2_IRQ_NB 8
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#define VIA2_IRQ_SCSI_DATA (1 << VIA2_IRQ_SCSI_DATA_BIT)
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#define VIA2_IRQ_NUBUS (1 << VIA2_IRQ_NUBUS_BIT)
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#define VIA2_IRQ_UNUSED (1 << VIA2_IRQ_SCSI_BIT)
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#define VIA2_IRQ_SCSI (1 << VIA2_IRQ_UNUSED_BIT)
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#define VIA2_IRQ_ASC (1 << VIA2_IRQ_ASC_BIT)
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#define VIA2_IRQ_SCSI_DATA BIT(VIA2_IRQ_SCSI_DATA_BIT)
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#define VIA2_IRQ_NUBUS BIT(VIA2_IRQ_NUBUS_BIT)
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#define VIA2_IRQ_UNUSED BIT(VIA2_IRQ_SCSI_BIT)
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#define VIA2_IRQ_SCSI BIT(VIA2_IRQ_UNUSED_BIT)
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#define VIA2_IRQ_ASC BIT(VIA2_IRQ_ASC_BIT)
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#define VIA2_NUBUS_IRQ_NB 7
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@ -193,8 +193,6 @@ struct PMUState {
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MemoryRegion mem;
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uint64_t frequency;
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qemu_irq via_irq;
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bool via_irq_state;
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/* PMU state */
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MOS6522PMUState mos6522_pmu;
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@ -32,6 +32,8 @@
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#include "hw/input/adb.h"
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#include "qom/object.h"
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#define MOS6522_NUM_REGS 16
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/* Bits in ACR */
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#define SR_CTRL 0x1c /* Shift register control bits */
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#define SR_EXT 0x0c /* Shift on external clock */
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@ -41,18 +43,43 @@
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#define IER_SET 0x80 /* set bits in IER */
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#define IER_CLR 0 /* clear bits in IER */
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#define CA2_INT 0x01
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#define CA1_INT 0x02
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#define SR_INT 0x04 /* Shift register full/empty */
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#define CB2_INT 0x08
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#define CB1_INT 0x10
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#define T2_INT 0x20 /* Timer 2 interrupt */
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#define T1_INT 0x40 /* Timer 1 interrupt */
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#define CA2_INT_BIT 0
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#define CA1_INT_BIT 1
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#define SR_INT_BIT 2 /* Shift register full/empty */
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#define CB2_INT_BIT 3
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#define CB1_INT_BIT 4
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#define T2_INT_BIT 5 /* Timer 2 interrupt */
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#define T1_INT_BIT 6 /* Timer 1 interrupt */
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#define CA2_INT BIT(CA2_INT_BIT)
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#define CA1_INT BIT(CA1_INT_BIT)
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#define SR_INT BIT(SR_INT_BIT)
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#define CB2_INT BIT(CB2_INT_BIT)
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#define CB1_INT BIT(CB1_INT_BIT)
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#define T2_INT BIT(T2_INT_BIT)
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#define T1_INT BIT(T1_INT_BIT)
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#define VIA_NUM_INTS 5
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/* Bits in ACR */
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#define T1MODE 0xc0 /* Timer 1 mode */
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#define T1MODE_CONT 0x40 /* continuous interrupts */
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/* Bits in PCR */
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#define CB2_CTRL_MASK 0xe0
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#define CB2_CTRL_SHIFT 5
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#define CB1_CTRL_MASK 0x10
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#define CB1_CTRL_SHIFT 4
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#define CA2_CTRL_MASK 0x0e
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#define CA2_CTRL_SHIFT 1
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#define CA1_CTRL_MASK 0x1
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#define CA1_CTRL_SHIFT 0
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#define C2_POS 0x2
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#define C2_IND 0x1
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#define C1_POS 0x1
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/* VIA registers */
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#define VIA_REG_B 0x00
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#define VIA_REG_A 0x01
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@ -121,6 +148,7 @@ struct MOS6522State {
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uint64_t frequency;
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qemu_irq irq;
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uint8_t last_irq_levels;
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};
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#define TYPE_MOS6522 "mos6522"
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@ -130,10 +158,8 @@ struct MOS6522DeviceClass {
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DeviceClass parent_class;
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DeviceReset parent_reset;
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void (*set_sr_int)(MOS6522State *dev);
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void (*portB_write)(MOS6522State *dev);
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void (*portA_write)(MOS6522State *dev);
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void (*update_irq)(MOS6522State *dev);
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/* These are used to influence the CUDA MacOS timebase calibration */
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uint64_t (*get_timer1_counter_value)(MOS6522State *dev, MOS6522Timer *ti);
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uint64_t (*get_timer2_counter_value)(MOS6522State *dev, MOS6522Timer *ti);
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@ -147,4 +173,6 @@ extern const VMStateDescription vmstate_mos6522;
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uint64_t mos6522_read(void *opaque, hwaddr addr, unsigned size);
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void mos6522_write(void *opaque, hwaddr addr, uint64_t val, unsigned size);
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void hmp_info_via(Monitor *mon, const QDict *qdict);
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#endif /* MOS6522_H */
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@ -51,7 +51,7 @@ struct ESPState {
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ESPDMAMemoryReadWriteFunc dma_memory_write;
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void *dma_opaque;
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void (*dma_cb)(ESPState *s);
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void (*pdma_cb)(ESPState *s);
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uint8_t pdma_cb;
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uint8_t mig_version_id;
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@ -150,6 +150,15 @@ struct SysBusESPState {
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#define TCHI_FAS100A 0x4
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#define TCHI_AM53C974 0x12
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/* PDMA callbacks */
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enum pdma_cb {
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SATN_PDMA_CB = 0,
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S_WITHOUT_SATN_PDMA_CB = 1,
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SATN_STOP_PDMA_CB = 2,
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WRITE_RESPONSE_PDMA_CB = 3,
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DO_DMA_PDMA_CB = 4
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};
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void esp_dma_enable(ESPState *s, int irq, int level);
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void esp_request_cancelled(SCSIRequest *req);
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void esp_command_complete(SCSIRequest *req, size_t resid);
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