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hw/mem: Stubbed out NPCM7xx Memory Controller model

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This just implements the bare minimum to cause the boot block to skip
memory initialization.

Reviewed-by: Tyrone Ting <kfting@nuvoton.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Alexander Bulekov <alxndr@bu.edu>
Signed-off-by: Havard Skinnemoen <hskinnemoen@google.com>
Message-id: 20200911052101.2602693-10-hskinnemoen@google.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Havard Skinnemoen 2020-09-10 22:20:56 -07:00 • committed by Peter Maydell
parent c752bb079b
commit 1351f89246
5 changed files with 129 additions and 0 deletions
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1
hw/mem/meson.build
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@ -1,6 +1,7 @@
mem_ss = ss.source_set()
mem_ss.add(files('memory-device.c'))
mem_ss.add(when: 'CONFIG_DIMM', if_true: files('pc-dimm.c'))
mem_ss.add(when: 'CONFIG_NPCM7XX', if_true: files('npcm7xx_mc.c'))
mem_ss.add(when: 'CONFIG_NVDIMM', if_true: files('nvdimm.c'))
softmmu_ss.add_all(when: 'CONFIG_MEM_DEVICE', if_true: mem_ss)

84
hw/mem/npcm7xx_mc.c Normal file
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@ -0,0 +1,84 @@
/*
* Nuvoton NPCM7xx Memory Controller stub
*
* Copyright 2020 Google LLC
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* for more details.
*/
#include "qemu/osdep.h"
#include "hw/mem/npcm7xx_mc.h"
#include "qapi/error.h"
#include "qemu/log.h"
#include "qemu/module.h"
#include "qemu/units.h"
#define NPCM7XX_MC_REGS_SIZE (4 * KiB)
static uint64_t npcm7xx_mc_read(void *opaque, hwaddr addr, unsigned int size)
{
/*
* If bits 8..11 @ offset 0 are not zero, the boot block thinks the memory
* controller has already been initialized and will skip DDR training.
*/
if (addr == 0) {
return 0x100;
}
qemu_log_mask(LOG_UNIMP, "%s: mostly unimplemented\n", __func__);
return 0;
}
static void npcm7xx_mc_write(void *opaque, hwaddr addr, uint64_t v,
unsigned int size)
{
qemu_log_mask(LOG_UNIMP, "%s: mostly unimplemented\n", __func__);
}
static const MemoryRegionOps npcm7xx_mc_ops = {
.read = npcm7xx_mc_read,
.write = npcm7xx_mc_write,
.endianness = DEVICE_LITTLE_ENDIAN,
.valid = {
.min_access_size = 4,
.max_access_size = 4,
.unaligned = false,
},
};
static void npcm7xx_mc_realize(DeviceState *dev, Error **errp)
{
NPCM7xxMCState *s = NPCM7XX_MC(dev);
memory_region_init_io(&s->mmio, OBJECT(s), &npcm7xx_mc_ops, s, "regs",
NPCM7XX_MC_REGS_SIZE);
sysbus_init_mmio(&s->parent, &s->mmio);
}
static void npcm7xx_mc_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
dc->desc = "NPCM7xx Memory Controller stub";
dc->realize = npcm7xx_mc_realize;
}
static const TypeInfo npcm7xx_mc_types[] = {
{
.name = TYPE_NPCM7XX_MC,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(NPCM7xxMCState),
.class_init = npcm7xx_mc_class_init,
},
};
DEFINE_TYPES(npcm7xx_mc_types);