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RISC-V: Adding XTheadSync ISA extension

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This patch adds support for the XTheadSync ISA extension.
The patch uses the T-Head specific decoder and translation.

The implementation introduces a helper to execute synchronization tasks:
helper_tlb_flush_all() performs a synchronized TLB flush on all CPUs.

Co-developed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
Message-Id: <20230131202013.2541053-3-christoph.muellner@vrull.eu>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Christoph Müllner 2023-01-31 21:20:01 +01:00 • committed by Alistair Francis
parent 49a7f3aabb
commit 134c3ffa34
7 changed files with 105 additions and 1 deletions
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9
target/riscv/xthead.decode
View file

@ -10,9 +10,11 @@
# Fields:
%rs1 15:5
%rs2 20:5
# Formats
@sfence_vm ....... ..... ..... ... ..... ....... %rs1
@rs2_s ....... ..... ..... ... ..... ....... %rs2 %rs1
# XTheadCmo
th_dcache_call 0000000 00001 00000 000 00000 0001011
@ -36,3 +38,10 @@ th_icache_iva 0000001 10000 ..... 000 00000 0001011 @sfence_vm
th_l2cache_call 0000000 10101 00000 000 00000 0001011
th_l2cache_ciall 0000000 10111 00000 000 00000 0001011
th_l2cache_iall 0000000 10110 00000 000 00000 0001011
# XTheadSync
th_sfence_vmas 0000010 ..... ..... 000 00000 0001011 @rs2_s
th_sync 0000000 11000 00000 000 00000 0001011
th_sync_i 0000000 11010 00000 000 00000 0001011
th_sync_is 0000000 11011 00000 000 00000 0001011
th_sync_s 0000000 11001 00000 000 00000 0001011