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RISC-V: Adding XTheadSync ISA extension

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This patch adds support for the XTheadSync ISA extension.
The patch uses the T-Head specific decoder and translation.

The implementation introduces a helper to execute synchronization tasks:
helper_tlb_flush_all() performs a synchronized TLB flush on all CPUs.

Co-developed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
Message-Id: <20230131202013.2541053-3-christoph.muellner@vrull.eu>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Christoph Müllner 2023-01-31 21:20:01 +01:00 • committed by Alistair Francis
parent 49a7f3aabb
commit 134c3ffa34
7 changed files with 105 additions and 1 deletions
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85
target/riscv/insn_trans/trans_xthead.c.inc
View file

@ -22,6 +22,12 @@
} \
} while (0)
#define REQUIRE_XTHEADSYNC(ctx) do { \
if (!ctx->cfg_ptr->ext_xtheadsync) { \
return false; \
} \
} while (0)
/* XTheadCmo */
static inline int priv_level(DisasContext *ctx)
@ -79,3 +85,82 @@ NOP_PRIVCHECK(th_icache_iva, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MSU)
NOP_PRIVCHECK(th_l2cache_call, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MS)
NOP_PRIVCHECK(th_l2cache_ciall, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MS)
NOP_PRIVCHECK(th_l2cache_iall, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MS)
/* XTheadSync */
static bool trans_th_sfence_vmas(DisasContext *ctx, arg_th_sfence_vmas *a)
{
(void) a;
REQUIRE_XTHEADSYNC(ctx);
#ifndef CONFIG_USER_ONLY
REQUIRE_PRIV_MS(ctx);
gen_helper_tlb_flush_all(cpu_env);
return true;
#else
return false;
#endif
}
#ifndef CONFIG_USER_ONLY
static void gen_th_sync_local(DisasContext *ctx)
{
/*
* Emulate out-of-order barriers with pipeline flush
* by exiting the translation block.
*/
gen_set_pc_imm(ctx, ctx->pc_succ_insn);
tcg_gen_exit_tb(NULL, 0);
ctx->base.is_jmp = DISAS_NORETURN;
}
#endif
static bool trans_th_sync(DisasContext *ctx, arg_th_sync *a)
{
(void) a;
REQUIRE_XTHEADSYNC(ctx);
#ifndef CONFIG_USER_ONLY
REQUIRE_PRIV_MSU(ctx);
/*
* th.sync is an out-of-order barrier.
*/
gen_th_sync_local(ctx);
return true;
#else
return false;
#endif
}
static bool trans_th_sync_i(DisasContext *ctx, arg_th_sync_i *a)
{
(void) a;
REQUIRE_XTHEADSYNC(ctx);
#ifndef CONFIG_USER_ONLY
REQUIRE_PRIV_MSU(ctx);
/*
* th.sync.i is th.sync plus pipeline flush.
*/
gen_th_sync_local(ctx);
return true;
#else
return false;
#endif
}
static bool trans_th_sync_is(DisasContext *ctx, arg_th_sync_is *a)
{
/* This instruction has the same behaviour like th.sync.i. */
return trans_th_sync_i(ctx, a);
}
static bool trans_th_sync_s(DisasContext *ctx, arg_th_sync_s *a)
{
/* This instruction has the same behaviour like th.sync. */
return trans_th_sync(ctx, a);
}