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hw/block/nvme: add remaining mandatory controller parameters
Add support for any remaining mandatory controller operating parameters (features). Signed-off-by: Klaus Jensen <k.jensen@samsung.com> Reviewed-by: Dmitry Fomichev <dmitry.fomichev@wdc.com> Reviewed-by: Maxim Levitsky <mlevitsk@redhat.com> Message-Id: <20200706061303.246057-12-its@irrelevant.dk>
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3 changed files with 61 additions and 7 deletions
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@ -85,6 +85,20 @@
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" in %s: " fmt "\n", __func__, ## __VA_ARGS__); \
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} while (0)
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static const bool nvme_feature_support[NVME_FID_MAX] = {
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[NVME_ARBITRATION] = true,
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[NVME_POWER_MANAGEMENT] = true,
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[NVME_TEMPERATURE_THRESHOLD] = true,
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[NVME_ERROR_RECOVERY] = true,
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[NVME_VOLATILE_WRITE_CACHE] = true,
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[NVME_NUMBER_OF_QUEUES] = true,
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[NVME_INTERRUPT_COALESCING] = true,
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[NVME_INTERRUPT_VECTOR_CONF] = true,
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[NVME_WRITE_ATOMICITY] = true,
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[NVME_ASYNCHRONOUS_EVENT_CONF] = true,
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[NVME_TIMESTAMP] = true,
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};
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static void nvme_process_sq(void *opaque);
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static uint16_t nvme_cid(NvmeRequest *req)
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@ -1085,8 +1099,20 @@ static uint16_t nvme_get_feature(NvmeCtrl *n, NvmeCmd *cmd, NvmeRequest *req)
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uint32_t dw10 = le32_to_cpu(cmd->cdw10);
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uint32_t dw11 = le32_to_cpu(cmd->cdw11);
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uint32_t result;
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uint8_t fid = NVME_GETSETFEAT_FID(dw10);
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uint16_t iv;
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switch (dw10) {
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static const uint32_t nvme_feature_default[NVME_FID_MAX] = {
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[NVME_ARBITRATION] = NVME_ARB_AB_NOLIMIT,
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};
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trace_pci_nvme_getfeat(nvme_cid(req), fid, dw11);
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if (!nvme_feature_support[fid]) {
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return NVME_INVALID_FIELD | NVME_DNR;
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}
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switch (fid) {
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case NVME_TEMPERATURE_THRESHOLD:
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result = 0;
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@ -1116,6 +1142,18 @@ static uint16_t nvme_get_feature(NvmeCtrl *n, NvmeCmd *cmd, NvmeRequest *req)
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result = (n->params.max_ioqpairs - 1) |
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((n->params.max_ioqpairs - 1) << 16);
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trace_pci_nvme_getfeat_numq(result);
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break;
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case NVME_INTERRUPT_VECTOR_CONF:
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iv = dw11 & 0xffff;
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if (iv >= n->params.max_ioqpairs + 1) {
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return NVME_INVALID_FIELD | NVME_DNR;
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}
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result = iv;
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if (iv == n->admin_cq.vector) {
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result |= NVME_INTVC_NOCOALESCING;
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}
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break;
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case NVME_ASYNCHRONOUS_EVENT_CONF:
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result = n->features.async_config;
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@ -1123,8 +1161,8 @@ static uint16_t nvme_get_feature(NvmeCtrl *n, NvmeCmd *cmd, NvmeRequest *req)
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case NVME_TIMESTAMP:
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return nvme_get_feature_timestamp(n, cmd);
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default:
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trace_pci_nvme_err_invalid_getfeat(dw10);
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return NVME_INVALID_FIELD | NVME_DNR;
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result = nvme_feature_default[fid];
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break;
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}
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req->cqe.result = cpu_to_le32(result);
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@ -1153,8 +1191,15 @@ static uint16_t nvme_set_feature(NvmeCtrl *n, NvmeCmd *cmd, NvmeRequest *req)
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{
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uint32_t dw10 = le32_to_cpu(cmd->cdw10);
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uint32_t dw11 = le32_to_cpu(cmd->cdw11);
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uint8_t fid = NVME_GETSETFEAT_FID(dw10);
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switch (dw10) {
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trace_pci_nvme_setfeat(nvme_cid(req), fid, dw11);
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if (!nvme_feature_support[fid]) {
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return NVME_INVALID_FIELD | NVME_DNR;
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}
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switch (fid) {
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case NVME_TEMPERATURE_THRESHOLD:
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if (NVME_TEMP_TMPSEL(dw11) != NVME_TEMP_TMPSEL_COMPOSITE) {
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break;
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@ -1201,8 +1246,7 @@ static uint16_t nvme_set_feature(NvmeCtrl *n, NvmeCmd *cmd, NvmeRequest *req)
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case NVME_TIMESTAMP:
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return nvme_set_feature_timestamp(n, cmd);
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default:
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trace_pci_nvme_err_invalid_setfeat(dw10);
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return NVME_INVALID_FIELD | NVME_DNR;
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return NVME_FEAT_NOT_CHANGEABLE | NVME_DNR;
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}
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return NVME_SUCCESS;
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}
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@ -46,6 +46,8 @@ pci_nvme_identify_ctrl(void) "identify controller"
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pci_nvme_identify_ns(uint32_t ns) "nsid %"PRIu32""
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pci_nvme_identify_nslist(uint32_t ns) "nsid %"PRIu32""
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pci_nvme_get_log(uint16_t cid, uint8_t lid, uint8_t lsp, uint8_t rae, uint32_t len, uint64_t off) "cid %"PRIu16" lid 0x%"PRIx8" lsp 0x%"PRIx8" rae 0x%"PRIx8" len %"PRIu32" off %"PRIu64""
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pci_nvme_getfeat(uint16_t cid, uint8_t fid, uint32_t cdw11) "cid %"PRIu16" fid 0x%"PRIx8" cdw11 0x%"PRIx32""
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pci_nvme_setfeat(uint16_t cid, uint8_t fid, uint32_t cdw11) "cid %"PRIu16" fid 0x%"PRIx8" cdw11 0x%"PRIx32""
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pci_nvme_getfeat_vwcache(const char* result) "get feature volatile write cache, result=%s"
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pci_nvme_getfeat_numq(int result) "get feature number of queues, result=%d"
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pci_nvme_setfeat_numq(int reqcq, int reqsq, int gotcq, int gotsq) "requested cq_count=%d sq_count=%d, responding with cq_count=%d sq_count=%d"
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