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qom: Have class_init() take a const data argument

Browse source 
Mechanical change using gsed, then style manually adapted
to pass checkpatch.pl script.

Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20250424194905.82506-4-philmd@linaro.org>
This commit is contained in:
Philippe Mathieu-Daudé 2025-02-09 23:47:35 +01:00
parent f1fa787b92
commit 12d1a768bd
1121 changed files with 1774 additions and 1707 deletions
Download patch file Download diff file Expand all files Collapse all files

6
hw/pci-host/articia.c
View file

@ -195,7 +195,7 @@ static void articia_realize(DeviceState *dev, Error **errp)
qdev_init_gpio_out(dev, s->irq, ARRAY_SIZE(s->irq));
}
static void articia_class_init(ObjectClass *klass, void *data)
static void articia_class_init(ObjectClass *klass, const void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
@ -228,7 +228,7 @@ static void articia_pci_host_cfg_write(PCIDevice *d, uint32_t addr,
}
}
static void articia_pci_host_class_init(ObjectClass *klass, void *data)
static void articia_pci_host_class_init(ObjectClass *klass, const void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
@ -246,7 +246,7 @@ static void articia_pci_host_class_init(ObjectClass *klass, void *data)
/* TYPE_ARTICIA_PCI_BRIDGE */
static void articia_pci_bridge_class_init(ObjectClass *klass, void *data)
static void articia_pci_bridge_class_init(ObjectClass *klass, const void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);

6
hw/pci-host/astro.c
View file

@ -482,7 +482,7 @@ static const VMStateDescription vmstate_elroy = {
}
};
static void elroy_pcihost_class_init(ObjectClass *klass, void *data)
static void elroy_pcihost_class_init(ObjectClass *klass, const void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
@ -909,7 +909,7 @@ static void astro_realize(DeviceState *obj, Error **errp)
}
}
static void astro_class_init(ObjectClass *klass, void *data)
static void astro_class_init(ObjectClass *klass, const void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
@ -932,7 +932,7 @@ static const TypeInfo astro_chip_info = {
};
static void astro_iommu_memory_region_class_init(ObjectClass *klass,
void *data)
const void *data)
{
IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_CLASS(klass);

4
hw/pci-host/bonito.c
View file

@ -757,7 +757,7 @@ PCIBus *bonito_init(qemu_irq *pic)
return phb->bus;
}
static void bonito_pci_class_init(ObjectClass *klass, void *data)
static void bonito_pci_class_init(ObjectClass *klass, const void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
@ -789,7 +789,7 @@ static const TypeInfo bonito_pci_info = {
},
};
static void bonito_host_class_init(ObjectClass *klass, void *data)
static void bonito_host_class_init(ObjectClass *klass, const void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);

9
hw/pci-host/designware.c
View file

@ -56,7 +56,8 @@
#define DESIGNWARE_PCIE_ATU_DEVFN(x) (((x) >> 16) & 0xff)
#define DESIGNWARE_PCIE_ATU_UPPER_TARGET 0x91C
static void designware_pcie_root_bus_class_init(ObjectClass *klass, void *data)
static void designware_pcie_root_bus_class_init(ObjectClass *klass,
const void *data)
{
BusClass *k = BUS_CLASS(klass);
@ -587,7 +588,8 @@ static const VMStateDescription vmstate_designware_pcie_root = {
}
};
static void designware_pcie_root_class_init(ObjectClass *klass, void *data)
static void designware_pcie_root_class_init(ObjectClass *klass,
const void *data)
{
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
DeviceClass *dc = DEVICE_CLASS(klass);
@ -727,7 +729,8 @@ static const VMStateDescription vmstate_designware_pcie_host = {
}
};
static void designware_pcie_host_class_init(ObjectClass *klass, void *data)
static void designware_pcie_host_class_init(ObjectClass *klass,
const void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(klass);

2
hw/pci-host/dino.c
View file

@ -497,7 +497,7 @@ static const Property dino_pcihost_properties[] = {
MemoryRegion *),
};
static void dino_pcihost_class_init(ObjectClass *klass, void *data)
static void dino_pcihost_class_init(ObjectClass *klass, const void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);

2
hw/pci-host/fsl_imx8m_phy.c
View file

@ -76,7 +76,7 @@ static const VMStateDescription fsl_imx8m_pcie_phy_vmstate = {
}
};
static void fsl_imx8m_pcie_phy_class_init(ObjectClass *klass, void *data)
static void fsl_imx8m_pcie_phy_class_init(ObjectClass *klass, const void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
ResettableClass *rc = RESETTABLE_CLASS(klass);

4
hw/pci-host/gpex.c
View file

@ -192,7 +192,7 @@ static const Property gpex_host_properties[] = {
DEFINE_PROP_UINT8("num-irqs", GPEXHost, num_irqs, PCI_NUM_PINS),
};
static void gpex_host_class_init(ObjectClass *klass, void *data)
static void gpex_host_class_init(ObjectClass *klass, const void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(klass);
@ -237,7 +237,7 @@ static const VMStateDescription vmstate_gpex_root = {
}
};
static void gpex_root_class_init(ObjectClass *klass, void *data)
static void gpex_root_class_init(ObjectClass *klass, const void *data)
{
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
DeviceClass *dc = DEVICE_CLASS(klass);

4
hw/pci-host/grackle.c
View file

@ -94,7 +94,7 @@ static void grackle_pci_realize(PCIDevice *d, Error **errp)
d->config[PCI_CLASS_PROG] = 0x01;
}
static void grackle_pci_class_init(ObjectClass *klass, void *data)
static void grackle_pci_class_init(ObjectClass *klass, const void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
@ -133,7 +133,7 @@ static const Property grackle_properties[] = {
DEFINE_PROP_UINT32("ofw-addr", GrackleState, ofw_addr, -1),
};
static void grackle_class_init(ObjectClass *klass, void *data)
static void grackle_class_init(ObjectClass *klass, const void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
SysBusDeviceClass *sbc = SYS_BUS_DEVICE_CLASS(klass);

4
hw/pci-host/gt64120.c
View file

@ -1244,7 +1244,7 @@ static void gt64120_pci_reset_hold(Object *obj, ResetType type)
pci_set_byte(d->config + 0x3d, 0x01);
}
static void gt64120_pci_class_init(ObjectClass *klass, void *data)
static void gt64120_pci_class_init(ObjectClass *klass, const void *data)
{
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
DeviceClass *dc = DEVICE_CLASS(klass);
@ -1279,7 +1279,7 @@ static const Property gt64120_properties[] = {
cpu_little_endian, false),
};
static void gt64120_class_init(ObjectClass *klass, void *data)
static void gt64120_class_init(ObjectClass *klass, const void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);

4
hw/pci-host/i440fx.c
View file

@ -315,7 +315,7 @@ static void i440fx_pcihost_realize(DeviceState *dev, Error **errp)
i440fx_update_memory_mappings(f);
}
static void i440fx_class_init(ObjectClass *klass, void *data)
static void i440fx_class_init(ObjectClass *klass, const void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
@ -364,7 +364,7 @@ static const Property i440fx_props[] = {
DEFINE_PROP_STRING(I440FX_HOST_PROP_PCI_TYPE, I440FXState, pci_type),
};
static void i440fx_pcihost_class_init(ObjectClass *klass, void *data)
static void i440fx_pcihost_class_init(ObjectClass *klass, const void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(klass);

6
hw/pci-host/mv64361.c
View file

@ -26,7 +26,7 @@
#define TYPE_MV64361_PCI_BRIDGE "mv64361-pcibridge"
static void mv64361_pcibridge_class_init(ObjectClass *klass, void *data)
static void mv64361_pcibridge_class_init(ObjectClass *klass, const void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
@ -102,7 +102,7 @@ static const Property mv64361_pcihost_props[] = {
DEFINE_PROP_UINT8("index", MV64361PCIState, index, 0),
};
static void mv64361_pcihost_class_init(ObjectClass *klass, void *data)
static void mv64361_pcihost_class_init(ObjectClass *klass, const void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
@ -923,7 +923,7 @@ static void mv64361_reset(DeviceState *dev)
set_mem_windows(s, 0xfbfff);
}
static void mv64361_class_init(ObjectClass *klass, void *data)
static void mv64361_class_init(ObjectClass *klass, const void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);

4
hw/pci-host/pnv_phb.c
View file

@ -194,7 +194,7 @@ static const Property pnv_phb_properties[] = {
PnvPhb4PecState *),
};
static void pnv_phb_class_init(ObjectClass *klass, void *data)
static void pnv_phb_class_init(ObjectClass *klass, const void *data)
{
PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(klass);
DeviceClass *dc = DEVICE_CLASS(klass);
@ -304,7 +304,7 @@ static const Property pnv_phb_root_port_properties[] = {
DEFINE_PROP_UINT32("version", PnvPHBRootPort, version, 0),
};
static void pnv_phb_root_port_class_init(ObjectClass *klass, void *data)
static void pnv_phb_root_port_class_init(ObjectClass *klass, const void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
ResettableClass *rc = RESETTABLE_CLASS(klass);

6
hw/pci-host/pnv_phb3.c
View file

@ -888,7 +888,7 @@ DECLARE_INSTANCE_CHECKER(IOMMUMemoryRegion, PNV_PHB3_IOMMU_MEMORY_REGION,
TYPE_PNV_PHB3_IOMMU_MEMORY_REGION)
static void pnv_phb3_iommu_memory_region_class_init(ObjectClass *klass,
void *data)
const void *data)
{
IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_CLASS(klass);
@ -1097,7 +1097,7 @@ static const Property pnv_phb3_properties[] = {
DEFINE_PROP_LINK("phb-base", PnvPHB3, phb_base, TYPE_PNV_PHB, PnvPHB *),
};
static void pnv_phb3_class_init(ObjectClass *klass, void *data)
static void pnv_phb3_class_init(ObjectClass *klass, const void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
@ -1149,7 +1149,7 @@ static void pnv_phb3_root_bus_set_prop(Object *obj, Visitor *v,
}
}
static void pnv_phb3_root_bus_class_init(ObjectClass *klass, void *data)
static void pnv_phb3_root_bus_class_init(ObjectClass *klass, const void *data)
{
BusClass *k = BUS_CLASS(klass);

2
hw/pci-host/pnv_phb3_msi.c
View file

@ -284,7 +284,7 @@ static void phb3_msi_instance_init(Object *obj)
ics->offset = 0;
}
static void phb3_msi_class_init(ObjectClass *klass, void *data)
static void phb3_msi_class_init(ObjectClass *klass, const void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
ICSStateClass *isc = ICS_CLASS(klass);

2
hw/pci-host/pnv_phb3_pbcq.c
View file

@ -337,7 +337,7 @@ static void phb3_pbcq_instance_init(Object *obj)
OBJ_PROP_LINK_STRONG);
}
static void pnv_pbcq_class_init(ObjectClass *klass, void *data)
static void pnv_pbcq_class_init(ObjectClass *klass, const void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
PnvXScomInterfaceClass *xdc = PNV_XSCOM_INTERFACE_CLASS(klass);

6
hw/pci-host/pnv_phb4.c
View file

@ -1362,7 +1362,7 @@ DECLARE_INSTANCE_CHECKER(IOMMUMemoryRegion, PNV_PHB4_IOMMU_MEMORY_REGION,
TYPE_PNV_PHB4_IOMMU_MEMORY_REGION)
static void pnv_phb4_iommu_memory_region_class_init(ObjectClass *klass,
void *data)
const void *data)
{
IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_CLASS(klass);
@ -1696,7 +1696,7 @@ static const Property pnv_phb4_properties[] = {
DEFINE_PROP_LINK("phb-base", PnvPHB4, phb_base, TYPE_PNV_PHB, PnvPHB *),
};
static void pnv_phb4_class_init(ObjectClass *klass, void *data)
static void pnv_phb4_class_init(ObjectClass *klass, const void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
XiveNotifierClass *xfc = XIVE_NOTIFIER_CLASS(klass);
@ -1761,7 +1761,7 @@ static void pnv_phb4_root_bus_set_prop(Object *obj, Visitor *v,
}
}
static void pnv_phb4_root_bus_class_init(ObjectClass *klass, void *data)
static void pnv_phb4_root_bus_class_init(ObjectClass *klass, const void *data)
{
BusClass *k = BUS_CLASS(klass);

4
hw/pci-host/pnv_phb4_pec.c
View file

@ -354,7 +354,7 @@ static uint32_t pnv_pec_xscom_nest_base(PnvPhb4PecState *pec)
*/
static const uint32_t pnv_pec_num_phbs[] = { 1, 2, 3 };
static void pnv_pec_class_init(ObjectClass *klass, void *data)
static void pnv_pec_class_init(ObjectClass *klass, const void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
PnvXScomInterfaceClass *xdc = PNV_XSCOM_INTERFACE_CLASS(klass);
@ -419,7 +419,7 @@ static uint32_t pnv_phb5_pec_xscom_nest_base(PnvPhb4PecState *pec)
*/
static const uint32_t pnv_phb5_pec_num_stacks[] = { 3, 3 };
static void pnv_phb5_pec_class_init(ObjectClass *klass, void *data)
static void pnv_phb5_pec_class_init(ObjectClass *klass, const void *data)
{
PnvPhb4PecClass *pecc = PNV_PHB4_PEC_CLASS(klass);
static const char compat[] = "ibm,power10-pbcq";

2
hw/pci-host/ppc440_pcix.c
View file

@ -519,7 +519,7 @@ static void ppc440_pcix_realize(DeviceState *dev, Error **errp)
sysbus_init_mmio(sbd, &s->iomem);
}
static void ppc440_pcix_class_init(ObjectClass *klass, void *data)
static void ppc440_pcix_class_init(ObjectClass *klass, const void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);

4
hw/pci-host/ppc4xx_pci.c
View file

@ -349,7 +349,7 @@ static void ppc4xx_pcihost_realize(DeviceState *dev, Error **errp)
qemu_register_reset(ppc4xx_pci_reset, s);
}
static void ppc4xx_host_bridge_class_init(ObjectClass *klass, void *data)
static void ppc4xx_host_bridge_class_init(ObjectClass *klass, const void *data)
{
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
DeviceClass *dc = DEVICE_CLASS(klass);
@ -376,7 +376,7 @@ static const TypeInfo ppc4xx_host_bridge_info = {
},
};
static void ppc4xx_pcihost_class_init(ObjectClass *klass, void *data)
static void ppc4xx_pcihost_class_init(ObjectClass *klass, const void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);

4
hw/pci-host/ppce500.c
View file

@ -490,7 +490,7 @@ static void e500_pcihost_realize(DeviceState *dev, Error **errp)
pci_bus_set_route_irq_fn(b, e500_route_intx_pin_to_irq);
}
static void e500_host_bridge_class_init(ObjectClass *klass, void *data)
static void e500_host_bridge_class_init(ObjectClass *klass, const void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
@ -512,7 +512,7 @@ static const Property pcihost_properties[] = {
DEFINE_PROP_UINT32("first_pin_irq", PPCE500PCIState, first_pin_irq, 0x1),
};
static void e500_pcihost_class_init(ObjectClass *klass, void *data)
static void e500_pcihost_class_init(ObjectClass *klass, const void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);

4
hw/pci-host/q35.c
View file

@ -184,7 +184,7 @@ static const Property q35_host_props[] = {
DEFINE_PROP_BOOL("x-pci-hole64-fix", Q35PCIHost, pci_hole64_fix, true),
};
static void q35_host_class_init(ObjectClass *klass, void *data)
static void q35_host_class_init(ObjectClass *klass, const void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(klass);
@ -667,7 +667,7 @@ static const Property mch_props[] = {
DEFINE_PROP_BOOL("smbase-smram", MCHPCIState, has_smram_at_smbase, true),
};
static void mch_class_init(ObjectClass *klass, void *data)
static void mch_class_init(ObjectClass *klass, const void *data)
{
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
DeviceClass *dc = DEVICE_CLASS(klass);

4
hw/pci-host/raven.c
View file

@ -392,7 +392,7 @@ static const VMStateDescription vmstate_raven = {
},
};
static void raven_class_init(ObjectClass *klass, void *data)
static void raven_class_init(ObjectClass *klass, const void *data)
{
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
DeviceClass *dc = DEVICE_CLASS(klass);
@ -431,7 +431,7 @@ static const Property raven_pcihost_properties[] = {
false),
};
static void raven_pcihost_class_init(ObjectClass *klass, void *data)
static void raven_pcihost_class_init(ObjectClass *klass, const void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);

2
hw/pci-host/remote.c
View file

@ -46,7 +46,7 @@ static void remote_pcihost_realize(DeviceState *dev, Error **errp)
0, TYPE_PCIE_BUS);
}
static void remote_pcihost_class_init(ObjectClass *klass, void *data)
static void remote_pcihost_class_init(ObjectClass *klass, const void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(klass);

4
hw/pci-host/sabre.c
View file

@ -456,7 +456,7 @@ static void sabre_pci_realize(PCIDevice *d, Error **errp)
PCI_STATUS_DEVSEL_MEDIUM);
}
static void sabre_pci_class_init(ObjectClass *klass, void *data)
static void sabre_pci_class_init(ObjectClass *klass, const void *data)
{
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
DeviceClass *dc = DEVICE_CLASS(klass);
@ -497,7 +497,7 @@ static const Property sabre_properties[] = {
DEFINE_PROP_UINT64("mem-base", SabreState, mem_base, 0),
};
static void sabre_class_init(ObjectClass *klass, void *data)
static void sabre_class_init(ObjectClass *klass, const void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
SysBusDeviceClass *sbc = SYS_BUS_DEVICE_CLASS(klass);

4
hw/pci-host/sh_pci.c
View file

@ -153,7 +153,7 @@ static void sh_pcic_pci_realize(PCIDevice *d, Error **errp)
PCI_STATUS_FAST_BACK | PCI_STATUS_DEVSEL_MEDIUM);
}
static void sh_pcic_pci_class_init(ObjectClass *klass, void *data)
static void sh_pcic_pci_class_init(ObjectClass *klass, const void *data)
{
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
DeviceClass *dc = DEVICE_CLASS(klass);
@ -168,7 +168,7 @@ static void sh_pcic_pci_class_init(ObjectClass *klass, void *data)
dc->user_creatable = false;
}
static void sh_pcic_host_class_init(ObjectClass *klass, void *data)
static void sh_pcic_host_class_init(ObjectClass *klass, const void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);

19
hw/pci-host/uninorth.c
View file

@ -311,7 +311,7 @@ static void unin_internal_pci_host_realize(PCIDevice *d, Error **errp)
d->config[PCI_CAPABILITY_LIST] = 0x00;
}
static void unin_main_pci_host_class_init(ObjectClass *klass, void *data)
static void unin_main_pci_host_class_init(ObjectClass *klass, const void *data)
{
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
DeviceClass *dc = DEVICE_CLASS(klass);
@ -339,7 +339,7 @@ static const TypeInfo unin_main_pci_host_info = {
},
};
static void u3_agp_pci_host_class_init(ObjectClass *klass, void *data)
static void u3_agp_pci_host_class_init(ObjectClass *klass, const void *data)
{
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
DeviceClass *dc = DEVICE_CLASS(klass);
@ -367,7 +367,7 @@ static const TypeInfo u3_agp_pci_host_info = {
},
};
static void unin_agp_pci_host_class_init(ObjectClass *klass, void *data)
static void unin_agp_pci_host_class_init(ObjectClass *klass, const void *data)
{
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
DeviceClass *dc = DEVICE_CLASS(klass);
@ -395,7 +395,8 @@ static const TypeInfo unin_agp_pci_host_info = {
},
};
static void unin_internal_pci_host_class_init(ObjectClass *klass, void *data)
static void unin_internal_pci_host_class_init(ObjectClass *klass,
const void *data)
{
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
DeviceClass *dc = DEVICE_CLASS(klass);
@ -427,7 +428,7 @@ static const Property pci_unin_main_pci_host_props[] = {
DEFINE_PROP_UINT32("ofw-addr", UNINHostState, ofw_addr, -1),
};
static void pci_unin_main_class_init(ObjectClass *klass, void *data)
static void pci_unin_main_class_init(ObjectClass *klass, const void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
SysBusDeviceClass *sbc = SYS_BUS_DEVICE_CLASS(klass);
@ -447,7 +448,7 @@ static const TypeInfo pci_unin_main_info = {
.class_init = pci_unin_main_class_init,
};
static void pci_u3_agp_class_init(ObjectClass *klass, void *data)
static void pci_u3_agp_class_init(ObjectClass *klass, const void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
@ -463,7 +464,7 @@ static const TypeInfo pci_u3_agp_info = {
.class_init = pci_u3_agp_class_init,
};
static void pci_unin_agp_class_init(ObjectClass *klass, void *data)
static void pci_unin_agp_class_init(ObjectClass *klass, const void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
@ -479,7 +480,7 @@ static const TypeInfo pci_unin_agp_info = {
.class_init = pci_unin_agp_class_init,
};
static void pci_unin_internal_class_init(ObjectClass *klass, void *data)
static void pci_unin_internal_class_init(ObjectClass *klass, const void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
@ -535,7 +536,7 @@ static void unin_init(Object *obj)
sysbus_init_mmio(sbd, &s->mem);
}
static void unin_class_init(ObjectClass *klass, void *data)
static void unin_class_init(ObjectClass *klass, const void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);

4
hw/pci-host/versatile.c
View file

@ -471,7 +471,7 @@ static void versatile_pci_host_realize(PCIDevice *d, Error **errp)
pci_set_byte(d->config + PCI_LATENCY_TIMER, 0x10);
}
static void versatile_pci_host_class_init(ObjectClass *klass, void *data)
static void versatile_pci_host_class_init(ObjectClass *klass, const void *data)
{
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
DeviceClass *dc = DEVICE_CLASS(klass);
@ -503,7 +503,7 @@ static const Property pci_vpb_properties[] = {
PCI_VPB_IRQMAP_ASSUME_OK),
};
static void pci_vpb_class_init(ObjectClass *klass, void *data)
static void pci_vpb_class_init(ObjectClass *klass, const void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);

3
hw/pci-host/xen_igd_pt.c
View file

@ -95,7 +95,8 @@ static void igd_pt_i440fx_realize(PCIDevice *pci_dev, Error **errp)
}
}
static void igd_passthrough_i440fx_class_init(ObjectClass *klass, void *data)
static void igd_passthrough_i440fx_class_init(ObjectClass *klass,
const void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);

4
hw/pci-host/xilinx-pcie.c
View file

@ -165,7 +165,7 @@ static const Property xilinx_pcie_host_props[] = {
DEFINE_PROP_BOOL("link_up", XilinxPCIEHost, link_up, true),
};
static void xilinx_pcie_host_class_init(ObjectClass *klass, void *data)
static void xilinx_pcie_host_class_init(ObjectClass *klass, const void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(klass);
@ -286,7 +286,7 @@ static void xilinx_pcie_root_realize(PCIDevice *pci_dev, Error **errp)
}
}
static void xilinx_pcie_root_class_init(ObjectClass *klass, void *data)
static void xilinx_pcie_root_class_init(ObjectClass *klass, const void *data)
{
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
DeviceClass *dc = DEVICE_CLASS(klass);