mirror of
https://github.com/Motorhead1991/qemu.git
synced 2025-08-01 23:03:54 -06:00
ich9: implement SMI_LOCK
Add write mask for the smi enable register, so we can disable write access to certain bits. Open all bits on reset. Disable write access to GBL_SMI_EN when SMI_LOCK (in ich9 lpc pci config space) is set. Write access to SMI_LOCK itself is disabled too. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Acked-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
This commit is contained in:
parent
bafc90bdc5
commit
11e66a15a0
4 changed files with 29 additions and 1 deletions
|
@ -39,6 +39,7 @@ typedef struct ICH9LPCPMRegs {
|
|||
MemoryRegion io_smi;
|
||||
|
||||
uint32_t smi_en;
|
||||
uint32_t smi_en_wmask;
|
||||
uint32_t smi_sts;
|
||||
|
||||
qemu_irq irq; /* SCI */
|
||||
|
|
|
@ -152,6 +152,12 @@ Object *ich9_lpc_find(void);
|
|||
#define ICH9_LPC_PIRQ_ROUT_MASK Q35_MASK(8, 3, 0)
|
||||
#define ICH9_LPC_PIRQ_ROUT_DEFAULT 0x80
|
||||
|
||||
#define ICH9_LPC_GEN_PMCON_1 0xa0
|
||||
#define ICH9_LPC_GEN_PMCON_1_SMI_LOCK (1 << 4)
|
||||
#define ICH9_LPC_GEN_PMCON_2 0xa2
|
||||
#define ICH9_LPC_GEN_PMCON_3 0xa4
|
||||
#define ICH9_LPC_GEN_PMCON_LOCK 0xa6
|
||||
|
||||
#define ICH9_LPC_RCBA 0xf0
|
||||
#define ICH9_LPC_RCBA_BA_MASK Q35_MASK(32, 31, 14)
|
||||
#define ICH9_LPC_RCBA_EN 0x1
|
||||
|
|
Loading…
Add table
Add a link
Reference in a new issue