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target-arm: A64: add support for B and BL insns

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Implement the B and BL instructions (PC relative branches and calls).

For convenience in managing TCG temporaries which might be generated
if a source register is the zero-register XZR, we provide a simple
mechanism for creating a new temp which is automatically freed at the
end of decode of the instruction.

Signed-off-by: Alexander Graf <agraf@suse.de>
[claudio: renamed functions, adapted to new decoder layout]
Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
This commit is contained in:
Alexander Graf 2013-12-17 19:42:32 +00:00 • committed by Peter Maydell
parent 87462e0f41
commit 11e169de99
2 changed files with 65 additions and 2 deletions
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3
target-arm/translate.h
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@ -24,6 +24,9 @@ typedef struct DisasContext {
int vec_len;
int vec_stride;
int aarch64;
#define TMP_A64_MAX 16
int tmp_a64_count;
TCGv_i64 tmp_a64[TMP_A64_MAX];
} DisasContext;
extern TCGv_ptr cpu_env;