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target/microblaze: Remove LOG_DIS

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Also remove the related defines, DISAS_MB and DEBUG_DISAS.
Rely on print_insn_microblaze.

Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2020-08-17 21:08:40 -07:00
parent e3f8d192e0
commit 11105d6749
1 changed files with 1 additions and 77 deletions
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78
target/microblaze/translate.c
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@ -33,14 +33,6 @@
#include "trace-tcg.h" #include "trace-tcg.h"
#include "exec/log.h" #include "exec/log.h"
#define DISAS_MB 1
#if DISAS_MB
# define LOG_DIS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
#else
# define LOG_DIS(...) do { } while (0)
#endif
#define EXTRACT_FIELD(src, start, end) \ #define EXTRACT_FIELD(src, start, end) \
(((src) >> start) & ((1 << (end - start + 1)) - 1)) (((src) >> start) & ((1 << (end - start + 1)) - 1))
@ -205,10 +197,6 @@ static void dec_add(DisasContext *dc)
k = dc->opcode & 4; k = dc->opcode & 4;
c = dc->opcode & 2; c = dc->opcode & 2;
LOG_DIS("add%s%s%s r%d r%d r%d\n",
dc->type_b ? "i" : "", k ? "k" : "", c ? "c" : "",
dc->rd, dc->ra, dc->rb);
/* Take care of the easy cases first. */ /* Take care of the easy cases first. */
if (k) { if (k) {
/* k - keep carry, no need to update MSR. */ /* k - keep carry, no need to update MSR. */
@ -252,7 +240,6 @@ static void dec_sub(DisasContext *dc)
cmp = (dc->imm & 1) && (!dc->type_b) && k; cmp = (dc->imm & 1) && (!dc->type_b) && k;
if (cmp) { if (cmp) {
LOG_DIS("cmp%s r%d, r%d ir=%x\n", u ? "u" : "", dc->rd, dc->ra, dc->ir);
if (dc->rd) { if (dc->rd) {
if (u) if (u)
gen_helper_cmpu(cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]); gen_helper_cmpu(cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]);
@ -262,9 +249,6 @@ static void dec_sub(DisasContext *dc)
return; return;
} }
LOG_DIS("sub%s%s r%d, r%d r%d\n",
k ? "k" : "", c ? "c" : "", dc->rd, dc->ra, dc->rb);
/* Take care of the easy cases first. */ /* Take care of the easy cases first. */
if (k) { if (k) {
/* k - keep carry, no need to update MSR. */ /* k - keep carry, no need to update MSR. */
@ -314,19 +298,16 @@ static void dec_pattern(DisasContext *dc)
switch (mode) { switch (mode) {
case 0: case 0:
/* pcmpbf. */ /* pcmpbf. */
LOG_DIS("pcmpbf r%d r%d r%d\n", dc->rd, dc->ra, dc->rb);
if (dc->rd) if (dc->rd)
gen_helper_pcmpbf(cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]); gen_helper_pcmpbf(cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]);
break; break;
case 2: case 2:
LOG_DIS("pcmpeq r%d r%d r%d\n", dc->rd, dc->ra, dc->rb);
if (dc->rd) { if (dc->rd) {
tcg_gen_setcond_i32(TCG_COND_EQ, cpu_R[dc->rd], tcg_gen_setcond_i32(TCG_COND_EQ, cpu_R[dc->rd],
cpu_R[dc->ra], cpu_R[dc->rb]); cpu_R[dc->ra], cpu_R[dc->rb]);
} }
break; break;
case 3: case 3:
LOG_DIS("pcmpne r%d r%d r%d\n", dc->rd, dc->ra, dc->rb);
if (dc->rd) { if (dc->rd) {
tcg_gen_setcond_i32(TCG_COND_NE, cpu_R[dc->rd], tcg_gen_setcond_i32(TCG_COND_NE, cpu_R[dc->rd],
cpu_R[dc->ra], cpu_R[dc->rb]); cpu_R[dc->ra], cpu_R[dc->rb]);
@ -349,7 +330,6 @@ static void dec_and(DisasContext *dc)
} }
not = dc->opcode & (1 << 1); not = dc->opcode & (1 << 1);
LOG_DIS("and%s\n", not ? "n" : "");
if (!dc->rd) if (!dc->rd)
return; return;
@ -367,7 +347,6 @@ static void dec_or(DisasContext *dc)
return; return;
} }
LOG_DIS("or r%d r%d r%d imm=%x\n", dc->rd, dc->ra, dc->rb, dc->imm);
if (dc->rd) if (dc->rd)
tcg_gen_or_i32(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc))); tcg_gen_or_i32(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc)));
} }
@ -379,7 +358,6 @@ static void dec_xor(DisasContext *dc)
return; return;
} }
LOG_DIS("xor r%d\n", dc->rd);
if (dc->rd) if (dc->rd)
tcg_gen_xor_i32(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc))); tcg_gen_xor_i32(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc)));
} }
@ -433,9 +411,6 @@ static void dec_msr(DisasContext *dc)
if (clrset) { if (clrset) {
bool clr = extract32(dc->ir, 16, 1); bool clr = extract32(dc->ir, 16, 1);
LOG_DIS("msr%s r%d imm=%x\n", clr ? "clr" : "set",
dc->rd, dc->imm);
if (!dc->cpu->cfg.use_msr_instr) { if (!dc->cpu->cfg.use_msr_instr) {
/* nop??? */ /* nop??? */
return; return;
@ -478,7 +453,6 @@ static void dec_msr(DisasContext *dc)
sr &= 7; sr &= 7;
tmp_sr = tcg_const_i32(sr); tmp_sr = tcg_const_i32(sr);
LOG_DIS("m%ss sr%d r%d imm=%x\n", to ? "t" : "f", sr, dc->ra, dc->imm);
if (to) { if (to) {
gen_helper_mmu_write(cpu_env, tmp_ext, tmp_sr, cpu_R[dc->ra]); gen_helper_mmu_write(cpu_env, tmp_ext, tmp_sr, cpu_R[dc->ra]);
} else { } else {
@ -491,7 +465,6 @@ static void dec_msr(DisasContext *dc)
#endif #endif
if (to) { if (to) {
LOG_DIS("m%ss sr%x r%d imm=%x\n", to ? "t" : "f", sr, dc->ra, dc->imm);
switch (sr) { switch (sr) {
case SR_PC: case SR_PC:
break; break;
@ -535,8 +508,6 @@ static void dec_msr(DisasContext *dc)
break; break;
} }
} else { } else {
LOG_DIS("m%ss r%d sr%x imm=%x\n", to ? "t" : "f", dc->rd, sr, dc->imm);
switch (sr) { switch (sr) {
case SR_PC: case SR_PC:
tcg_gen_movi_i32(cpu_R[dc->rd], dc->base.pc_next); tcg_gen_movi_i32(cpu_R[dc->rd], dc->base.pc_next);
@ -609,7 +580,6 @@ static void dec_mul(DisasContext *dc)
subcode = dc->imm & 3; subcode = dc->imm & 3;
if (dc->type_b) { if (dc->type_b) {
LOG_DIS("muli r%d r%d %x\n", dc->rd, dc->ra, dc->imm);
tcg_gen_mul_i32(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc))); tcg_gen_mul_i32(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc)));
return; return;
} }
@ -622,21 +592,17 @@ static void dec_mul(DisasContext *dc)
tmp = tcg_temp_new_i32(); tmp = tcg_temp_new_i32();
switch (subcode) { switch (subcode) {
case 0: case 0:
LOG_DIS("mul r%d r%d r%d\n", dc->rd, dc->ra, dc->rb);
tcg_gen_mul_i32(cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]); tcg_gen_mul_i32(cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]);
break; break;
case 1: case 1:
LOG_DIS("mulh r%d r%d r%d\n", dc->rd, dc->ra, dc->rb);
tcg_gen_muls2_i32(tmp, cpu_R[dc->rd], tcg_gen_muls2_i32(tmp, cpu_R[dc->rd],
cpu_R[dc->ra], cpu_R[dc->rb]); cpu_R[dc->ra], cpu_R[dc->rb]);
break; break;
case 2: case 2:
LOG_DIS("mulhsu r%d r%d r%d\n", dc->rd, dc->ra, dc->rb);
tcg_gen_mulsu2_i32(tmp, cpu_R[dc->rd], tcg_gen_mulsu2_i32(tmp, cpu_R[dc->rd],
cpu_R[dc->ra], cpu_R[dc->rb]); cpu_R[dc->ra], cpu_R[dc->rb]);
break; break;
case 3: case 3:
LOG_DIS("mulhu r%d r%d r%d\n", dc->rd, dc->ra, dc->rb);
tcg_gen_mulu2_i32(tmp, cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]); tcg_gen_mulu2_i32(tmp, cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]);
break; break;
default: default:
@ -652,7 +618,6 @@ static void dec_div(DisasContext *dc)
unsigned int u; unsigned int u;
u = dc->imm & 2; u = dc->imm & 2;
LOG_DIS("div\n");
if (trap_illegal(dc, !dc->cpu->cfg.use_div)) { if (trap_illegal(dc, !dc->cpu->cfg.use_div)) {
return; return;
@ -688,10 +653,6 @@ static void dec_barrel(DisasContext *dc)
imm_w = extract32(dc->imm, 6, 5); imm_w = extract32(dc->imm, 6, 5);
imm_s = extract32(dc->imm, 0, 5); imm_s = extract32(dc->imm, 0, 5);
LOG_DIS("bs%s%s%s r%d r%d r%d\n",
e ? "e" : "",
s ? "l" : "r", t ? "a" : "l", dc->rd, dc->ra, dc->rb);
if (e) { if (e) {
if (imm_w + imm_s > 32 || imm_w == 0) { if (imm_w + imm_s > 32 || imm_w == 0) {
/* These inputs have an undefined behavior. */ /* These inputs have an undefined behavior. */
@ -742,7 +703,6 @@ static void dec_bit(DisasContext *dc)
/* src. */ /* src. */
t0 = tcg_temp_new_i32(); t0 = tcg_temp_new_i32();
LOG_DIS("src r%d r%d\n", dc->rd, dc->ra);
tcg_gen_shli_i32(t0, cpu_msr_c, 31); tcg_gen_shli_i32(t0, cpu_msr_c, 31);
tcg_gen_andi_i32(cpu_msr_c, cpu_R[dc->ra], 1); tcg_gen_andi_i32(cpu_msr_c, cpu_R[dc->ra], 1);
if (dc->rd) { if (dc->rd) {
@ -755,8 +715,6 @@ static void dec_bit(DisasContext *dc)
case 0x1: case 0x1:
case 0x41: case 0x41:
/* srl. */ /* srl. */
LOG_DIS("srl r%d r%d\n", dc->rd, dc->ra);
tcg_gen_andi_i32(cpu_msr_c, cpu_R[dc->ra], 1); tcg_gen_andi_i32(cpu_msr_c, cpu_R[dc->ra], 1);
if (dc->rd) { if (dc->rd) {
if (op == 0x41) if (op == 0x41)
@ -766,11 +724,9 @@ static void dec_bit(DisasContext *dc)
} }
break; break;
case 0x60: case 0x60:
LOG_DIS("ext8s r%d r%d\n", dc->rd, dc->ra);
tcg_gen_ext8s_i32(cpu_R[dc->rd], cpu_R[dc->ra]); tcg_gen_ext8s_i32(cpu_R[dc->rd], cpu_R[dc->ra]);
break; break;
case 0x61: case 0x61:
LOG_DIS("ext16s r%d r%d\n", dc->rd, dc->ra);
tcg_gen_ext16s_i32(cpu_R[dc->rd], cpu_R[dc->ra]); tcg_gen_ext16s_i32(cpu_R[dc->rd], cpu_R[dc->ra]);
break; break;
case 0x64: case 0x64:
@ -778,12 +734,10 @@ static void dec_bit(DisasContext *dc)
case 0x74: case 0x74:
case 0x76: case 0x76:
/* wdc. */ /* wdc. */
LOG_DIS("wdc r%d\n", dc->ra);
trap_userspace(dc, true); trap_userspace(dc, true);
break; break;
case 0x68: case 0x68:
/* wic. */ /* wic. */
LOG_DIS("wic r%d\n", dc->ra);
trap_userspace(dc, true); trap_userspace(dc, true);
break; break;
case 0xe0: case 0xe0:
@ -796,12 +750,10 @@ static void dec_bit(DisasContext *dc)
break; break;
case 0x1e0: case 0x1e0:
/* swapb */ /* swapb */
LOG_DIS("swapb r%d r%d\n", dc->rd, dc->ra);
tcg_gen_bswap32_i32(cpu_R[dc->rd], cpu_R[dc->ra]); tcg_gen_bswap32_i32(cpu_R[dc->rd], cpu_R[dc->ra]);
break; break;
case 0x1e2: case 0x1e2:
/*swaph */ /*swaph */
LOG_DIS("swaph r%d r%d\n", dc->rd, dc->ra);
tcg_gen_rotri_i32(cpu_R[dc->rd], cpu_R[dc->ra], 16); tcg_gen_rotri_i32(cpu_R[dc->rd], cpu_R[dc->ra], 16);
break; break;
default: default:
@ -824,7 +776,6 @@ static inline void sync_jmpstate(DisasContext *dc)
static void dec_imm(DisasContext *dc) static void dec_imm(DisasContext *dc)
{ {
LOG_DIS("imm %x\n", dc->imm << 16);
tcg_gen_movi_i32(cpu_imm, (dc->imm << 16)); tcg_gen_movi_i32(cpu_imm, (dc->imm << 16));
dc->tb_flags |= IMM_FLAG; dc->tb_flags |= IMM_FLAG;
dc->clear_imm = 0; dc->clear_imm = 0;
@ -928,10 +879,6 @@ static void dec_load(DisasContext *dc)
return; return;
} }
LOG_DIS("l%d%s%s%s%s\n", size, dc->type_b ? "i" : "", rev ? "r" : "",
ex ? "x" : "",
ea ? "ea" : "");
t_sync_flags(dc); t_sync_flags(dc);
addr = tcg_temp_new(); addr = tcg_temp_new();
compute_ldst_addr(dc, ea, addr); compute_ldst_addr(dc, ea, addr);
@ -1039,9 +986,6 @@ static void dec_store(DisasContext *dc)
trap_userspace(dc, ea); trap_userspace(dc, ea);
LOG_DIS("s%d%s%s%s%s\n", size, dc->type_b ? "i" : "", rev ? "r" : "",
ex ? "x" : "",
ea ? "ea" : "");
t_sync_flags(dc); t_sync_flags(dc);
/* If we get a fault on a dslot, the jmpstate better be in sync. */ /* If we get a fault on a dslot, the jmpstate better be in sync. */
sync_jmpstate(dc); sync_jmpstate(dc);
@ -1184,7 +1128,6 @@ static void dec_bcc(DisasContext *dc)
cc = EXTRACT_FIELD(dc->ir, 21, 23); cc = EXTRACT_FIELD(dc->ir, 21, 23);
dslot = dc->ir & (1 << 25); dslot = dc->ir & (1 << 25);
LOG_DIS("bcc%s r%d %x\n", dslot ? "d" : "", dc->ra, dc->imm);
dc->delayed_branch = 1; dc->delayed_branch = 1;
if (dslot) { if (dslot) {
@ -1217,8 +1160,6 @@ static void dec_br(DisasContext *dc)
if (mbar == 2 && dc->imm == 4) { if (mbar == 2 && dc->imm == 4) {
uint16_t mbar_imm = dc->rd; uint16_t mbar_imm = dc->rd;
LOG_DIS("mbar %d\n", mbar_imm);
/* Data access memory barrier. */ /* Data access memory barrier. */
if ((mbar_imm & 2) == 0) { if ((mbar_imm & 2) == 0) {
tcg_gen_mb(TCG_BAR_SC | TCG_MO_ALL); tcg_gen_mb(TCG_BAR_SC | TCG_MO_ALL);
@ -1228,8 +1169,6 @@ static void dec_br(DisasContext *dc)
if (mbar_imm & 16) { if (mbar_imm & 16) {
TCGv_i32 tmp_1; TCGv_i32 tmp_1;
LOG_DIS("sleep\n");
if (trap_userspace(dc, true)) { if (trap_userspace(dc, true)) {
/* Sleep is a privileged instruction. */ /* Sleep is a privileged instruction. */
return; return;
@ -1253,11 +1192,6 @@ static void dec_br(DisasContext *dc)
return; return;
} }
LOG_DIS("br%s%s%s%s imm=%x\n",
abs ? "a" : "", link ? "l" : "",
dc->type_b ? "i" : "", dslot ? "d" : "",
dc->imm);
dc->delayed_branch = 1; dc->delayed_branch = 1;
if (dslot) { if (dslot) {
dec_setup_dslot(dc); dec_setup_dslot(dc);
@ -1363,16 +1297,12 @@ static void dec_rts(DisasContext *dc)
dec_setup_dslot(dc); dec_setup_dslot(dc);
if (i_bit) { if (i_bit) {
LOG_DIS("rtid ir=%x\n", dc->ir);
dc->tb_flags |= DRTI_FLAG; dc->tb_flags |= DRTI_FLAG;
} else if (b_bit) { } else if (b_bit) {
LOG_DIS("rtbd ir=%x\n", dc->ir);
dc->tb_flags |= DRTB_FLAG; dc->tb_flags |= DRTB_FLAG;
} else if (e_bit) { } else if (e_bit) {
LOG_DIS("rted ir=%x\n", dc->ir);
dc->tb_flags |= DRTE_FLAG; dc->tb_flags |= DRTE_FLAG;
} else }
LOG_DIS("rts ir=%x\n", dc->ir);
dc->jmp = JMP_INDIRECT; dc->jmp = JMP_INDIRECT;
tcg_gen_movi_i32(cpu_btaken, 1); tcg_gen_movi_i32(cpu_btaken, 1);
@ -1505,9 +1435,6 @@ static void dec_stream(DisasContext *dc)
TCGv_i32 t_id, t_ctrl; TCGv_i32 t_id, t_ctrl;
int ctrl; int ctrl;
LOG_DIS("%s%s imm=%x\n", dc->rd ? "get" : "put",
dc->type_b ? "" : "d", dc->imm);
if (trap_userspace(dc, true)) { if (trap_userspace(dc, true)) {
return; return;
} }
@ -1565,7 +1492,6 @@ static inline void decode(DisasContext *dc, uint32_t ir)
int i; int i;
dc->ir = ir; dc->ir = ir;
LOG_DIS("%8.8x\t", dc->ir);
if (ir == 0) { if (ir == 0) {
trap_illegal(dc, dc->cpu->cfg.opcode_0_illegal); trap_illegal(dc, dc->cpu->cfg.opcode_0_illegal);
@ -1744,10 +1670,8 @@ static void mb_tr_tb_stop(DisasContextBase *dcb, CPUState *cs)
static void mb_tr_disas_log(const DisasContextBase *dcb, CPUState *cs) static void mb_tr_disas_log(const DisasContextBase *dcb, CPUState *cs)
{ {
#ifdef DEBUG_DISAS
qemu_log("IN: %s\n", lookup_symbol(dcb->pc_first)); qemu_log("IN: %s\n", lookup_symbol(dcb->pc_first));
log_target_disas(cs, dcb->pc_first, dcb->tb->size); log_target_disas(cs, dcb->pc_first, dcb->tb->size);
#endif
} }
static const TranslatorOps mb_tr_ops = { static const TranslatorOps mb_tr_ops = {