mirror of
https://github.com/Motorhead1991/qemu.git
synced 2025-08-05 16:53:55 -06:00
target/riscv: Add host cpu type
'host' type cpu is set isa to RV32 or RV64 simply, more isa info will obtain from KVM in kvm_arch_init_vcpu() Signed-off-by: Yifei Jiang <jiangyifei@huawei.com> Signed-off-by: Mingwang Li <limingwang@huawei.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Message-id: 20220112081329.1835-10-jiangyifei@huawei.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
parent
4eb471258b
commit
10f1ca27e0
2 changed files with 16 additions and 0 deletions
|
@ -235,6 +235,18 @@ static void rv32_imafcu_nommu_cpu_init(Object *obj)
|
|||
}
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_KVM)
|
||||
static void riscv_host_cpu_init(Object *obj)
|
||||
{
|
||||
CPURISCVState *env = &RISCV_CPU(obj)->env;
|
||||
#if defined(TARGET_RISCV32)
|
||||
set_misa(env, MXL_RV32, 0);
|
||||
#elif defined(TARGET_RISCV64)
|
||||
set_misa(env, MXL_RV64, 0);
|
||||
#endif
|
||||
}
|
||||
#endif
|
||||
|
||||
static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model)
|
||||
{
|
||||
ObjectClass *oc;
|
||||
|
@ -847,6 +859,9 @@ static const TypeInfo riscv_cpu_type_infos[] = {
|
|||
.class_init = riscv_cpu_class_init,
|
||||
},
|
||||
DEFINE_CPU(TYPE_RISCV_CPU_ANY, riscv_any_cpu_init),
|
||||
#if defined(CONFIG_KVM)
|
||||
DEFINE_CPU(TYPE_RISCV_CPU_HOST, riscv_host_cpu_init),
|
||||
#endif
|
||||
#if defined(TARGET_RISCV32)
|
||||
DEFINE_CPU(TYPE_RISCV_CPU_BASE32, rv32_base_cpu_init),
|
||||
DEFINE_CPU(TYPE_RISCV_CPU_IBEX, rv32_ibex_cpu_init),
|
||||
|
|
Loading…
Add table
Add a link
Reference in a new issue