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* Functional tests improvements

Browse source 
* Endianness improvements/clean-ups for the Microblaze machines
 * Remove obsolete -2.4 and -2.5 i440fx and q35 machine types and related code
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Merge tag 'pull-request-2025-05-30' of https://gitlab.com/thuth/qemu into staging

* Functional tests improvements
* Endianness improvements/clean-ups for the Microblaze machines
* Remove obsolete -2.4 and -2.5 i440fx and q35 machine types and related code

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# gpg: Signature made Fri 30 May 2025 07:45:20 EDT
# gpg:                using RSA key 27B88847EEE0250118F3EAB92ED9D774FE702DB5
# gpg:                issuer "thuth@redhat.com"
# gpg: Good signature from "Thomas Huth <th.huth@gmx.de>" [full]
# gpg:                 aka "Thomas Huth <thuth@redhat.com>" [full]
# gpg:                 aka "Thomas Huth <huth@tuxfamily.org>" [full]
# gpg:                 aka "Thomas Huth <th.huth@posteo.de>" [unknown]
# Primary key fingerprint: 27B8 8847 EEE0 2501 18F3  EAB9 2ED9 D774 FE70 2DB5

* tag 'pull-request-2025-05-30' of https://gitlab.com/thuth/qemu: (25 commits)
  tests/unit/test-util-sockets: fix mem-leak on error object
  hw/net/vmxnet3: Merge DeviceRealize in InstanceInit
  hw/net/vmxnet3: Remove VMXNET3_COMPAT_FLAG_DISABLE_PCIE definition
  hw/net/vmxnet3: Remove VMXNET3_COMPAT_FLAG_OLD_MSI_OFFSETS definition
  hw/scsi/vmw_pvscsi: Convert DeviceRealize -> InstanceInit
  hw/scsi/vmw_pvscsi: Remove PVSCSI_COMPAT_DISABLE_PCIE_BIT definition
  hw/scsi/vmw_pvscsi: Remove PVSCSI_COMPAT_OLD_PCI_CONFIGURATION definition
  hw/core/machine: Remove hw_compat_2_5[] array
  hw/nvram/fw_cfg: Remove legacy FW_CFG_ORDER_OVERRIDE
  hw/i386/x86: Remove X86MachineClass::save_tsc_khz field
  hw/i386/pc: Remove deprecated pc-q35-2.5 and pc-i440fx-2.5 machines
  hw/virtio/virtio-pci: Remove VIRTIO_PCI_FLAG_DISABLE_PCIE definition
  hw/virtio/virtio-pci: Remove VIRTIO_PCI_FLAG_MIGRATE_EXTRA definition
  hw/net/e1000: Remove unused E1000_FLAG_MAC flag
  hw/core/machine: Remove hw_compat_2_4[] array
  hw/i386/pc: Remove pc_compat_2_4[] array
  hw/i386/pc: Remove PCMachineClass::broken_reserved_end field
  hw/i386/pc: Remove deprecated pc-q35-2.4 and pc-i440fx-2.4 machines
  docs: Deprecate the qemu-system-microblazeel binary
  hw/microblaze: Remove the big-endian variants of ml605 and xlnx-zynqmp-pmu
  ...

Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
This commit is contained in:
Stefan Hajnoczi 2025-05-30 11:41:13 -04:00
commit 107215089d
31 changed files with 197 additions and 510 deletions
Download patch file Download diff file Expand all files Collapse all files

19
docs/about/deprecated.rst
View file

@ -315,12 +315,6 @@ deprecated; use the new name ``dtb-randomness`` instead. The new name
better reflects the way this property affects all random data within better reflects the way this property affects all random data within
the device tree blob, not just the ``kaslr-seed`` node. the device tree blob, not just the ``kaslr-seed`` node.
Big-Endian variants of MicroBlaze ``petalogix-ml605`` and ``xlnx-zynqmp-pmu`` machines (since 9.2)
''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''
Both ``petalogix-ml605`` and ``xlnx-zynqmp-pmu`` were added for little endian
CPUs. Big endian support is not tested.
Mips ``mipssim`` machine (since 10.0) Mips ``mipssim`` machine (since 10.0)
''''''''''''''''''''''''''''''''''''' '''''''''''''''''''''''''''''''''''''
@ -351,6 +345,19 @@ machine must ensure that they're setting the ``spike`` machine in the
command line (``-M spike``). command line (``-M spike``).
System emulator binaries
------------------------
``qemu-system-microblazeel`` (since 10.1)
'''''''''''''''''''''''''''''''''''''''''
The ``qemu-system-microblaze`` binary can emulate little-endian machines
now, too, so the separate binary ``qemu-system-microblazeel`` (with the
``el`` suffix) for little-endian targets is not required anymore. The
``petalogix-s3adsp1800`` machine can now be switched to little endian by
setting its ``endianness`` property to ``little``.
Backend options Backend options
--------------- ---------------

9
docs/about/removed-features.rst
View file

@ -1091,6 +1091,15 @@ This machine was removed because PPC 405 CPU have no known users,
firmware images are not available, OpenWRT dropped support in 2019, firmware images are not available, OpenWRT dropped support in 2019,
U-Boot in 2017, and Linux in 2024. U-Boot in 2017, and Linux in 2024.
Big-Endian variants of ``petalogix-ml605`` and ``xlnx-zynqmp-pmu`` machines (removed in 10.1)
'''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''
Both the MicroBlaze ``petalogix-ml605`` and ``xlnx-zynqmp-pmu`` machines
were added for little endian CPUs. Big endian support was never tested
and likely never worked. Starting with QEMU v10.1, the machines are now
only available as little-endian machines.
linux-user mode CPUs linux-user mode CPUs
-------------------- --------------------

14
hw/core/loader.c
View file

@ -1333,20 +1333,6 @@ void rom_set_fw(FWCfgState *f)
fw_cfg = f; fw_cfg = f;
} }
void rom_set_order_override(int order)
{
if (!fw_cfg)
return;
fw_cfg_set_order_override(fw_cfg, order);
}
void rom_reset_order_override(void)
{
if (!fw_cfg)
return;
fw_cfg_reset_order_override(fw_cfg);
}
void rom_transaction_begin(void) void rom_transaction_begin(void)
{ {
Rom *rom; Rom *rom;

18
hw/core/machine.c
View file

@ -285,24 +285,6 @@ GlobalProperty hw_compat_2_6[] = {
}; };
const size_t hw_compat_2_6_len = G_N_ELEMENTS(hw_compat_2_6); const size_t hw_compat_2_6_len = G_N_ELEMENTS(hw_compat_2_6);
GlobalProperty hw_compat_2_5[] = {
{ "isa-fdc", "fallback", "144" },
{ "pvscsi", "x-old-pci-configuration", "on" },
{ "pvscsi", "x-disable-pcie", "on" },
{ "vmxnet3", "x-old-msi-offsets", "on" },
{ "vmxnet3", "x-disable-pcie", "on" },
};
const size_t hw_compat_2_5_len = G_N_ELEMENTS(hw_compat_2_5);
GlobalProperty hw_compat_2_4[] = {
{ "e1000", "extra_mac_registers", "off" },
{ "virtio-pci", "x-disable-pcie", "on" },
{ "virtio-pci", "migrate-extra", "off" },
{ "fw_cfg_mem", "dma_enabled", "off" },
{ "fw_cfg_io", "dma_enabled", "off" }
};
const size_t hw_compat_2_4_len = G_N_ELEMENTS(hw_compat_2_4);
MachineState *current_machine; MachineState *current_machine;
static char *machine_get_kernel(Object *obj, Error **errp) static char *machine_get_kernel(Object *obj, Error **errp)

42
hw/i386/pc.c
View file

@ -260,28 +260,6 @@ GlobalProperty pc_compat_2_6[] = {
}; };
const size_t pc_compat_2_6_len = G_N_ELEMENTS(pc_compat_2_6); const size_t pc_compat_2_6_len = G_N_ELEMENTS(pc_compat_2_6);
GlobalProperty pc_compat_2_5[] = {};
const size_t pc_compat_2_5_len = G_N_ELEMENTS(pc_compat_2_5);
GlobalProperty pc_compat_2_4[] = {
PC_CPU_MODEL_IDS("2.4.0")
{ "Haswell-" TYPE_X86_CPU, "abm", "off" },
{ "Haswell-noTSX-" TYPE_X86_CPU, "abm", "off" },
{ "Broadwell-" TYPE_X86_CPU, "abm", "off" },
{ "Broadwell-noTSX-" TYPE_X86_CPU, "abm", "off" },
{ "host" "-" TYPE_X86_CPU, "host-cache-info", "on" },
{ TYPE_X86_CPU, "check", "off" },
{ "qemu64" "-" TYPE_X86_CPU, "sse4a", "on" },
{ "qemu64" "-" TYPE_X86_CPU, "abm", "on" },
{ "qemu64" "-" TYPE_X86_CPU, "popcnt", "on" },
{ "qemu32" "-" TYPE_X86_CPU, "popcnt", "on" },
{ "Opteron_G2" "-" TYPE_X86_CPU, "rdtscp", "on" },
{ "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "on" },
{ "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "on" },
{ "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "on", }
};
const size_t pc_compat_2_4_len = G_N_ELEMENTS(pc_compat_2_4);
/* /*
* @PC_FW_DATA: * @PC_FW_DATA:
* Size of the chunk of memory at the top of RAM for the BIOS ACPI tables * Size of the chunk of memory at the top of RAM for the BIOS ACPI tables
@ -1002,14 +980,13 @@ void pc_memory_init(PCMachineState *pcms,
if (machine->device_memory) { if (machine->device_memory) {
uint64_t *val = g_malloc(sizeof(*val)); uint64_t *val = g_malloc(sizeof(*val));
uint64_t res_mem_end = machine->device_memory->base; uint64_t res_mem_end;
if (!pcmc->broken_reserved_end) {
res_mem_end += memory_region_size(&machine->device_memory->mr);
}
if (pcms->cxl_devices_state.is_enabled) { if (pcms->cxl_devices_state.is_enabled) {
res_mem_end = cxl_resv_end; res_mem_end = cxl_resv_end;
} else {
res_mem_end = machine->device_memory->base
+ memory_region_size(&machine->device_memory->mr);
} }
*val = cpu_to_le64(ROUND_UP(res_mem_end, 1 * GiB)); *val = cpu_to_le64(ROUND_UP(res_mem_end, 1 * GiB));
fw_cfg_add_file(fw_cfg, "etc/reserved-memory-end", val, sizeof(*val)); fw_cfg_add_file(fw_cfg, "etc/reserved-memory-end", val, sizeof(*val));
@ -1047,9 +1024,7 @@ uint64_t pc_pci_hole64_start(void)
hole64_start = pc_get_cxl_range_end(pcms); hole64_start = pc_get_cxl_range_end(pcms);
} else if (pcmc->has_reserved_memory && (ms->ram_size < ms->maxram_size)) { } else if (pcmc->has_reserved_memory && (ms->ram_size < ms->maxram_size)) {
pc_get_device_memory_range(pcms, &hole64_start, &size); pc_get_device_memory_range(pcms, &hole64_start, &size);
if (!pcmc->broken_reserved_end) { hole64_start += size;
hole64_start += size;
}
} else { } else {
hole64_start = pc_above_4g_end(pcms); hole64_start = pc_above_4g_end(pcms);
} }
@ -1061,7 +1036,6 @@ DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus)
{ {
DeviceState *dev = NULL; DeviceState *dev = NULL;
rom_set_order_override(FW_CFG_ORDER_OVERRIDE_VGA);
if (pci_bus) { if (pci_bus) {
PCIDevice *pcidev = pci_vga_init(pci_bus); PCIDevice *pcidev = pci_vga_init(pci_bus);
dev = pcidev ? &pcidev->qdev : NULL; dev = pcidev ? &pcidev->qdev : NULL;
@ -1069,7 +1043,7 @@ DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus)
ISADevice *isadev = isa_vga_init(isa_bus); ISADevice *isadev = isa_vga_init(isa_bus);
dev = isadev ? DEVICE(isadev) : NULL; dev = isadev ? DEVICE(isadev) : NULL;
} }
rom_reset_order_override();
return dev; return dev;
} }
@ -1259,8 +1233,6 @@ void pc_nic_init(PCMachineClass *pcmc, ISABus *isa_bus, PCIBus *pci_bus)
bool default_is_ne2k = g_str_equal(mc->default_nic, TYPE_ISA_NE2000); bool default_is_ne2k = g_str_equal(mc->default_nic, TYPE_ISA_NE2000);
NICInfo *nd; NICInfo *nd;
rom_set_order_override(FW_CFG_ORDER_OVERRIDE_NIC);
while ((nd = qemu_find_nic_info(TYPE_ISA_NE2000, default_is_ne2k, NULL))) { while ((nd = qemu_find_nic_info(TYPE_ISA_NE2000, default_is_ne2k, NULL))) {
pc_init_ne2k_isa(isa_bus, nd, &error_fatal); pc_init_ne2k_isa(isa_bus, nd, &error_fatal);
} }
@ -1269,8 +1241,6 @@ void pc_nic_init(PCMachineClass *pcmc, ISABus *isa_bus, PCIBus *pci_bus)
if (pci_bus) { if (pci_bus) {
pci_init_nic_devices(pci_bus, mc->default_nic); pci_init_nic_devices(pci_bus, mc->default_nic);
} }
rom_reset_order_override();
} }
void pc_i8259_create(ISABus *isa_bus, qemu_irq *i8259_irqs) void pc_i8259_create(ISABus *isa_bus, qemu_irq *i8259_irqs)

26
hw/i386/pc_piix.c
View file

@ -778,32 +778,6 @@ static void pc_i440fx_machine_2_6_options(MachineClass *m)
DEFINE_I440FX_MACHINE(2, 6); DEFINE_I440FX_MACHINE(2, 6);
static void pc_i440fx_machine_2_5_options(MachineClass *m)
{
X86MachineClass *x86mc = X86_MACHINE_CLASS(m);
pc_i440fx_machine_2_6_options(m);
x86mc->save_tsc_khz = false;
m->legacy_fw_cfg_order = 1;
compat_props_add(m->compat_props, hw_compat_2_5, hw_compat_2_5_len);
compat_props_add(m->compat_props, pc_compat_2_5, pc_compat_2_5_len);
}
DEFINE_I440FX_MACHINE(2, 5);
static void pc_i440fx_machine_2_4_options(MachineClass *m)
{
PCMachineClass *pcmc = PC_MACHINE_CLASS(m);
pc_i440fx_machine_2_5_options(m);
m->hw_version = "2.4.0";
pcmc->broken_reserved_end = true;
compat_props_add(m->compat_props, hw_compat_2_4, hw_compat_2_4_len);
compat_props_add(m->compat_props, pc_compat_2_4, pc_compat_2_4_len);
}
DEFINE_I440FX_MACHINE(2, 4);
#ifdef CONFIG_ISAPC #ifdef CONFIG_ISAPC
static void isapc_machine_options(MachineClass *m) static void isapc_machine_options(MachineClass *m)
{ {

26
hw/i386/pc_q35.c
View file

@ -672,29 +672,3 @@ static void pc_q35_machine_2_6_options(MachineClass *m)
} }
DEFINE_Q35_MACHINE(2, 6); DEFINE_Q35_MACHINE(2, 6);
static void pc_q35_machine_2_5_options(MachineClass *m)
{
X86MachineClass *x86mc = X86_MACHINE_CLASS(m);
pc_q35_machine_2_6_options(m);
x86mc->save_tsc_khz = false;
m->legacy_fw_cfg_order = 1;
compat_props_add(m->compat_props, hw_compat_2_5, hw_compat_2_5_len);
compat_props_add(m->compat_props, pc_compat_2_5, pc_compat_2_5_len);
}
DEFINE_Q35_MACHINE(2, 5);
static void pc_q35_machine_2_4_options(MachineClass *m)
{
PCMachineClass *pcmc = PC_MACHINE_CLASS(m);
pc_q35_machine_2_5_options(m);
m->hw_version = "2.4.0";
pcmc->broken_reserved_end = true;
compat_props_add(m->compat_props, hw_compat_2_4, hw_compat_2_4_len);
compat_props_add(m->compat_props, pc_compat_2_4, pc_compat_2_4_len);
}
DEFINE_Q35_MACHINE(2, 4);

1
hw/i386/x86.c
View file

@ -382,7 +382,6 @@ static void x86_machine_class_init(ObjectClass *oc, const void *data)
mc->get_default_cpu_node_id = x86_get_default_cpu_node_id; mc->get_default_cpu_node_id = x86_get_default_cpu_node_id;
mc->possible_cpu_arch_ids = x86_possible_cpu_arch_ids; mc->possible_cpu_arch_ids = x86_possible_cpu_arch_ids;
mc->kvm_type = x86_kvm_type; mc->kvm_type = x86_kvm_type;
x86mc->save_tsc_khz = true;
x86mc->fwcfg_dma_enabled = true; x86mc->fwcfg_dma_enabled = true;
nc->nmi_monitor_handler = x86_nmi; nc->nmi_monitor_handler = x86_nmi;

15
hw/microblaze/petalogix_ml605_mmu.c
View file

@ -80,8 +80,6 @@ petalogix_ml605_init(MachineState *machine)
MemoryRegion *phys_lmb_bram = g_new(MemoryRegion, 1); MemoryRegion *phys_lmb_bram = g_new(MemoryRegion, 1);
MemoryRegion *phys_ram = g_new(MemoryRegion, 1); MemoryRegion *phys_ram = g_new(MemoryRegion, 1);
qemu_irq irq[32]; qemu_irq irq[32];
EndianMode endianness = TARGET_BIG_ENDIAN ? ENDIAN_MODE_BIG
: ENDIAN_MODE_LITTLE;
/* init CPUs */ /* init CPUs */
cpu = MICROBLAZE_CPU(object_new(TYPE_MICROBLAZE_CPU)); cpu = MICROBLAZE_CPU(object_new(TYPE_MICROBLAZE_CPU));
@ -113,7 +111,7 @@ petalogix_ml605_init(MachineState *machine)
dev = qdev_new("xlnx.xps-intc"); dev = qdev_new("xlnx.xps-intc");
qdev_prop_set_enum(dev, "endianness", endianness); qdev_prop_set_enum(dev, "endianness", ENDIAN_MODE_LITTLE);
qdev_prop_set_uint32(dev, "kind-of-intr", 1 << TIMER_IRQ); qdev_prop_set_uint32(dev, "kind-of-intr", 1 << TIMER_IRQ);
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, INTC_BASEADDR); sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, INTC_BASEADDR);
@ -129,7 +127,7 @@ petalogix_ml605_init(MachineState *machine)
/* 2 timers at irq 2 @ 100 Mhz. */ /* 2 timers at irq 2 @ 100 Mhz. */
dev = qdev_new("xlnx.xps-timer"); dev = qdev_new("xlnx.xps-timer");
qdev_prop_set_enum(dev, "endianness", endianness); qdev_prop_set_enum(dev, "endianness", ENDIAN_MODE_LITTLE);
qdev_prop_set_uint32(dev, "one-timer-only", 0); qdev_prop_set_uint32(dev, "one-timer-only", 0);
qdev_prop_set_uint32(dev, "clock-frequency", 100 * 1000000); qdev_prop_set_uint32(dev, "clock-frequency", 100 * 1000000);
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
@ -177,7 +175,7 @@ petalogix_ml605_init(MachineState *machine)
SSIBus *spi; SSIBus *spi;
dev = qdev_new("xlnx.xps-spi"); dev = qdev_new("xlnx.xps-spi");
qdev_prop_set_enum(dev, "endianness", endianness); qdev_prop_set_enum(dev, "endianness", ENDIAN_MODE_LITTLE);
qdev_prop_set_uint8(dev, "num-ss-bits", NUM_SPI_FLASHES); qdev_prop_set_uint8(dev, "num-ss-bits", NUM_SPI_FLASHES);
busdev = SYS_BUS_DEVICE(dev); busdev = SYS_BUS_DEVICE(dev);
sysbus_realize_and_unref(busdev, &error_fatal); sysbus_realize_and_unref(busdev, &error_fatal);
@ -218,12 +216,7 @@ petalogix_ml605_init(MachineState *machine)
static void petalogix_ml605_machine_init(MachineClass *mc) static void petalogix_ml605_machine_init(MachineClass *mc)
{ {
if (TARGET_BIG_ENDIAN) { mc->desc = "PetaLogix linux refdesign for xilinx ml605 (little endian)";
mc->desc = "PetaLogix linux refdesign for xilinx ml605 (big endian)";
mc->deprecation_reason = "big endian support is not tested";
} else {
mc->desc = "PetaLogix linux refdesign for xilinx ml605 (little endian)";
}
mc->init = petalogix_ml605_init; mc->init = petalogix_ml605_init;
} }

42
hw/microblaze/petalogix_s3adsp1800_mmu.c
View file

@ -58,9 +58,20 @@
#define TYPE_PETALOGIX_S3ADSP1800_MACHINE \ #define TYPE_PETALOGIX_S3ADSP1800_MACHINE \
MACHINE_TYPE_NAME("petalogix-s3adsp1800") MACHINE_TYPE_NAME("petalogix-s3adsp1800")
struct S3Adsp1800MachineState {
MachineState parent_class;
EndianMode endianness;
};
OBJECT_DECLARE_TYPE(S3Adsp1800MachineState, MachineClass,
PETALOGIX_S3ADSP1800_MACHINE)
static void static void
petalogix_s3adsp1800_init(MachineState *machine) petalogix_s3adsp1800_init(MachineState *machine)
{ {
S3Adsp1800MachineState *psms = PETALOGIX_S3ADSP1800_MACHINE(machine);
ram_addr_t ram_size = machine->ram_size; ram_addr_t ram_size = machine->ram_size;
DeviceState *dev; DeviceState *dev;
MicroBlazeCPU *cpu; MicroBlazeCPU *cpu;
@ -71,13 +82,12 @@ petalogix_s3adsp1800_init(MachineState *machine)
MemoryRegion *phys_ram = g_new(MemoryRegion, 1); MemoryRegion *phys_ram = g_new(MemoryRegion, 1);
qemu_irq irq[32]; qemu_irq irq[32];
MemoryRegion *sysmem = get_system_memory(); MemoryRegion *sysmem = get_system_memory();
EndianMode endianness = TARGET_BIG_ENDIAN ? ENDIAN_MODE_BIG EndianMode endianness = psms->endianness;
: ENDIAN_MODE_LITTLE;
cpu = MICROBLAZE_CPU(object_new(TYPE_MICROBLAZE_CPU)); cpu = MICROBLAZE_CPU(object_new(TYPE_MICROBLAZE_CPU));
object_property_set_str(OBJECT(cpu), "version", "7.10.d", &error_abort); object_property_set_str(OBJECT(cpu), "version", "7.10.d", &error_abort);
object_property_set_bool(OBJECT(cpu), "little-endian", object_property_set_bool(OBJECT(cpu), "little-endian",
!TARGET_BIG_ENDIAN, &error_abort); endianness == ENDIAN_MODE_LITTLE, &error_abort);
qdev_realize(DEVICE(cpu), NULL, &error_abort); qdev_realize(DEVICE(cpu), NULL, &error_abort);
/* Attach emulated BRAM through the LMB. */ /* Attach emulated BRAM through the LMB. */
@ -135,20 +145,41 @@ petalogix_s3adsp1800_init(MachineState *machine)
create_unimplemented_device("xps_gpio", GPIO_BASEADDR, 0x10000); create_unimplemented_device("xps_gpio", GPIO_BASEADDR, 0x10000);
microblaze_load_kernel(cpu, !TARGET_BIG_ENDIAN, ddr_base, ram_size, microblaze_load_kernel(cpu, endianness == ENDIAN_MODE_LITTLE, ddr_base,
machine->initrd_filename, ram_size, machine->initrd_filename,
BINARY_DEVICE_TREE_FILE, BINARY_DEVICE_TREE_FILE,
NULL); NULL);
} }
static int machine_get_endianness(Object *obj, Error **errp G_GNUC_UNUSED)
{
S3Adsp1800MachineState *ms = PETALOGIX_S3ADSP1800_MACHINE(obj);
return ms->endianness;
}
static void machine_set_endianness(Object *obj, int endianness, Error **errp)
{
S3Adsp1800MachineState *ms = PETALOGIX_S3ADSP1800_MACHINE(obj);
ms->endianness = endianness;
}
static void petalogix_s3adsp1800_machine_class_init(ObjectClass *oc, static void petalogix_s3adsp1800_machine_class_init(ObjectClass *oc,
const void *data) const void *data)
{ {
MachineClass *mc = MACHINE_CLASS(oc); MachineClass *mc = MACHINE_CLASS(oc);
ObjectProperty *prop;
mc->desc = "PetaLogix linux refdesign for xilinx Spartan 3ADSP1800"; mc->desc = "PetaLogix linux refdesign for xilinx Spartan 3ADSP1800";
mc->init = petalogix_s3adsp1800_init; mc->init = petalogix_s3adsp1800_init;
mc->is_default = true; mc->is_default = true;
prop = object_class_property_add_enum(oc, "endianness", "EndianMode",
&EndianMode_lookup,
machine_get_endianness,
machine_set_endianness);
object_property_set_default_str(prop, TARGET_BIG_ENDIAN ? "big" : "little");
object_class_property_set_description(oc, "endianness",
"Defines whether the machine runs in big or little endian mode");
} }
static const TypeInfo petalogix_s3adsp1800_machine_types[] = { static const TypeInfo petalogix_s3adsp1800_machine_types[] = {
@ -156,6 +187,7 @@ static const TypeInfo petalogix_s3adsp1800_machine_types[] = {
.name = TYPE_PETALOGIX_S3ADSP1800_MACHINE, .name = TYPE_PETALOGIX_S3ADSP1800_MACHINE,
.parent = TYPE_MACHINE, .parent = TYPE_MACHINE,
.class_init = petalogix_s3adsp1800_machine_class_init, .class_init = petalogix_s3adsp1800_machine_class_init,
.instance_size = sizeof(S3Adsp1800MachineState),
}, },
}; };

7
hw/microblaze/xlnx-zynqmp-pmu.c
View file

@ -181,12 +181,7 @@ static void xlnx_zynqmp_pmu_init(MachineState *machine)
static void xlnx_zynqmp_pmu_machine_init(MachineClass *mc) static void xlnx_zynqmp_pmu_machine_init(MachineClass *mc)
{ {
if (TARGET_BIG_ENDIAN) { mc->desc = "Xilinx ZynqMP PMU machine (little endian)";
mc->desc = "Xilinx ZynqMP PMU machine (big endian)";
mc->deprecation_reason = "big endian support is not tested";
} else {
mc->desc = "Xilinx ZynqMP PMU machine (little endian)";
}
mc->init = xlnx_zynqmp_pmu_init; mc->init = xlnx_zynqmp_pmu_init;
} }

93
hw/net/e1000.c
View file

@ -127,10 +127,8 @@ struct E1000State_st {
QEMUTimer *flush_queue_timer; QEMUTimer *flush_queue_timer;
/* Compatibility flags for migration to/from qemu 1.3.0 and older */ /* Compatibility flags for migration to/from qemu 1.3.0 and older */
#define E1000_FLAG_MAC_BIT 2
#define E1000_FLAG_TSO_BIT 3 #define E1000_FLAG_TSO_BIT 3
#define E1000_FLAG_VET_BIT 4 #define E1000_FLAG_VET_BIT 4
#define E1000_FLAG_MAC (1 << E1000_FLAG_MAC_BIT)
#define E1000_FLAG_TSO (1 << E1000_FLAG_TSO_BIT) #define E1000_FLAG_TSO (1 << E1000_FLAG_TSO_BIT)
#define E1000_FLAG_VET (1 << E1000_FLAG_VET_BIT) #define E1000_FLAG_VET (1 << E1000_FLAG_VET_BIT)
@ -1212,52 +1210,51 @@ enum { NWRITEOPS = ARRAY_SIZE(macreg_writeops) };
enum { MAC_ACCESS_PARTIAL = 1, MAC_ACCESS_FLAG_NEEDED = 2 }; enum { MAC_ACCESS_PARTIAL = 1, MAC_ACCESS_FLAG_NEEDED = 2 };
#define markflag(x) ((E1000_FLAG_##x << 2) | MAC_ACCESS_FLAG_NEEDED)
/* In the array below the meaning of the bits is: [f|f|f|f|f|f|n|p] /* In the array below the meaning of the bits is: [f|f|f|f|f|f|n|p]
* f - flag bits (up to 6 possible flags) * f - flag bits (up to 6 possible flags)
* n - flag needed * n - flag needed
* p - partially implenented */ * p - partially implemented */
static const uint8_t mac_reg_access[0x8000] = { static const uint8_t mac_reg_access[0x8000] = {
[IPAV] = markflag(MAC), [WUC] = markflag(MAC), [IPAV] = MAC_ACCESS_FLAG_NEEDED, [WUC] = MAC_ACCESS_FLAG_NEEDED,
[IP6AT] = markflag(MAC), [IP4AT] = markflag(MAC), [IP6AT] = MAC_ACCESS_FLAG_NEEDED, [IP4AT] = MAC_ACCESS_FLAG_NEEDED,
[FFVT] = markflag(MAC), [WUPM] = markflag(MAC), [FFVT] = MAC_ACCESS_FLAG_NEEDED, [WUPM] = MAC_ACCESS_FLAG_NEEDED,
[ECOL] = markflag(MAC), [MCC] = markflag(MAC), [ECOL] = MAC_ACCESS_FLAG_NEEDED, [MCC] = MAC_ACCESS_FLAG_NEEDED,
[DC] = markflag(MAC), [TNCRS] = markflag(MAC), [DC] = MAC_ACCESS_FLAG_NEEDED, [TNCRS] = MAC_ACCESS_FLAG_NEEDED,
[RLEC] = markflag(MAC), [XONRXC] = markflag(MAC), [RLEC] = MAC_ACCESS_FLAG_NEEDED, [XONRXC] = MAC_ACCESS_FLAG_NEEDED,
[XOFFTXC] = markflag(MAC), [RFC] = markflag(MAC), [XOFFTXC] = MAC_ACCESS_FLAG_NEEDED, [RFC] = MAC_ACCESS_FLAG_NEEDED,
[TSCTFC] = markflag(MAC), [MGTPRC] = markflag(MAC), [TSCTFC] = MAC_ACCESS_FLAG_NEEDED, [MGTPRC] = MAC_ACCESS_FLAG_NEEDED,
[WUS] = markflag(MAC), [AIT] = markflag(MAC), [WUS] = MAC_ACCESS_FLAG_NEEDED, [AIT] = MAC_ACCESS_FLAG_NEEDED,
[FFLT] = markflag(MAC), [FFMT] = markflag(MAC), [FFLT] = MAC_ACCESS_FLAG_NEEDED, [FFMT] = MAC_ACCESS_FLAG_NEEDED,
[SCC] = markflag(MAC), [FCRUC] = markflag(MAC), [SCC] = MAC_ACCESS_FLAG_NEEDED, [FCRUC] = MAC_ACCESS_FLAG_NEEDED,
[LATECOL] = markflag(MAC), [COLC] = markflag(MAC), [LATECOL] = MAC_ACCESS_FLAG_NEEDED, [COLC] = MAC_ACCESS_FLAG_NEEDED,
[SEQEC] = markflag(MAC), [CEXTERR] = markflag(MAC), [SEQEC] = MAC_ACCESS_FLAG_NEEDED, [CEXTERR] = MAC_ACCESS_FLAG_NEEDED,
[XONTXC] = markflag(MAC), [XOFFRXC] = markflag(MAC), [XONTXC] = MAC_ACCESS_FLAG_NEEDED, [XOFFRXC] = MAC_ACCESS_FLAG_NEEDED,
[RJC] = markflag(MAC), [RNBC] = markflag(MAC), [RJC] = MAC_ACCESS_FLAG_NEEDED, [RNBC] = MAC_ACCESS_FLAG_NEEDED,
[MGTPDC] = markflag(MAC), [MGTPTC] = markflag(MAC), [MGTPDC] = MAC_ACCESS_FLAG_NEEDED, [MGTPTC] = MAC_ACCESS_FLAG_NEEDED,
[RUC] = markflag(MAC), [ROC] = markflag(MAC), [RUC] = MAC_ACCESS_FLAG_NEEDED, [ROC] = MAC_ACCESS_FLAG_NEEDED,
[GORCL] = markflag(MAC), [GORCH] = markflag(MAC), [GORCL] = MAC_ACCESS_FLAG_NEEDED, [GORCH] = MAC_ACCESS_FLAG_NEEDED,
[GOTCL] = markflag(MAC), [GOTCH] = markflag(MAC), [GOTCL] = MAC_ACCESS_FLAG_NEEDED, [GOTCH] = MAC_ACCESS_FLAG_NEEDED,
[BPRC] = markflag(MAC), [MPRC] = markflag(MAC), [BPRC] = MAC_ACCESS_FLAG_NEEDED, [MPRC] = MAC_ACCESS_FLAG_NEEDED,
[TSCTC] = markflag(MAC), [PRC64] = markflag(MAC), [TSCTC] = MAC_ACCESS_FLAG_NEEDED, [PRC64] = MAC_ACCESS_FLAG_NEEDED,
[PRC127] = markflag(MAC), [PRC255] = markflag(MAC), [PRC127] = MAC_ACCESS_FLAG_NEEDED, [PRC255] = MAC_ACCESS_FLAG_NEEDED,
[PRC511] = markflag(MAC), [PRC1023] = markflag(MAC), [PRC511] = MAC_ACCESS_FLAG_NEEDED, [PRC1023] = MAC_ACCESS_FLAG_NEEDED,
[PRC1522] = markflag(MAC), [PTC64] = markflag(MAC), [PRC1522] = MAC_ACCESS_FLAG_NEEDED, [PTC64] = MAC_ACCESS_FLAG_NEEDED,
[PTC127] = markflag(MAC), [PTC255] = markflag(MAC), [PTC127] = MAC_ACCESS_FLAG_NEEDED, [PTC255] = MAC_ACCESS_FLAG_NEEDED,
[PTC511] = markflag(MAC), [PTC1023] = markflag(MAC), [PTC511] = MAC_ACCESS_FLAG_NEEDED, [PTC1023] = MAC_ACCESS_FLAG_NEEDED,
[PTC1522] = markflag(MAC), [MPTC] = markflag(MAC), [PTC1522] = MAC_ACCESS_FLAG_NEEDED, [MPTC] = MAC_ACCESS_FLAG_NEEDED,
[BPTC] = markflag(MAC), [BPTC] = MAC_ACCESS_FLAG_NEEDED,
[TDFH] = markflag(MAC) | MAC_ACCESS_PARTIAL, [TDFH] = MAC_ACCESS_FLAG_NEEDED | MAC_ACCESS_PARTIAL,
[TDFT] = markflag(MAC) | MAC_ACCESS_PARTIAL, [TDFT] = MAC_ACCESS_FLAG_NEEDED | MAC_ACCESS_PARTIAL,
[TDFHS] = markflag(MAC) | MAC_ACCESS_PARTIAL, [TDFHS] = MAC_ACCESS_FLAG_NEEDED | MAC_ACCESS_PARTIAL,
[TDFTS] = markflag(MAC) | MAC_ACCESS_PARTIAL, [TDFTS] = MAC_ACCESS_FLAG_NEEDED | MAC_ACCESS_PARTIAL,
[TDFPC] = markflag(MAC) | MAC_ACCESS_PARTIAL, [TDFPC] = MAC_ACCESS_FLAG_NEEDED | MAC_ACCESS_PARTIAL,
[RDFH] = markflag(MAC) | MAC_ACCESS_PARTIAL, [RDFH] = MAC_ACCESS_FLAG_NEEDED | MAC_ACCESS_PARTIAL,
[RDFT] = markflag(MAC) | MAC_ACCESS_PARTIAL, [RDFT] = MAC_ACCESS_FLAG_NEEDED | MAC_ACCESS_PARTIAL,
[RDFHS] = markflag(MAC) | MAC_ACCESS_PARTIAL, [RDFHS] = MAC_ACCESS_FLAG_NEEDED | MAC_ACCESS_PARTIAL,
[RDFTS] = markflag(MAC) | MAC_ACCESS_PARTIAL, [RDFTS] = MAC_ACCESS_FLAG_NEEDED | MAC_ACCESS_PARTIAL,
[RDFPC] = markflag(MAC) | MAC_ACCESS_PARTIAL, [RDFPC] = MAC_ACCESS_FLAG_NEEDED | MAC_ACCESS_PARTIAL,
[PBM] = markflag(MAC) | MAC_ACCESS_PARTIAL, [PBM] = MAC_ACCESS_FLAG_NEEDED | MAC_ACCESS_PARTIAL,
}; };
static void static void
@ -1419,13 +1416,6 @@ static int e1000_tx_tso_post_load(void *opaque, int version_id)
return 0; return 0;
} }
static bool e1000_full_mac_needed(void *opaque)
{
E1000State *s = opaque;
return chkflag(MAC);
}
static bool e1000_tso_state_needed(void *opaque) static bool e1000_tso_state_needed(void *opaque)
{ {
E1000State *s = opaque; E1000State *s = opaque;
@ -1451,7 +1441,6 @@ static const VMStateDescription vmstate_e1000_full_mac_state = {
.name = "e1000/full_mac_state", .name = "e1000/full_mac_state",
.version_id = 1, .version_id = 1,
.minimum_version_id = 1, .minimum_version_id = 1,
.needed = e1000_full_mac_needed,
.fields = (const VMStateField[]) { .fields = (const VMStateField[]) {
VMSTATE_UINT32_ARRAY(mac_reg, E1000State, 0x8000), VMSTATE_UINT32_ARRAY(mac_reg, E1000State, 0x8000),
VMSTATE_END_OF_LIST() VMSTATE_END_OF_LIST()
@ -1679,8 +1668,6 @@ static void pci_e1000_realize(PCIDevice *pci_dev, Error **errp)
static const Property e1000_properties[] = { static const Property e1000_properties[] = {
DEFINE_NIC_PROPERTIES(E1000State, conf), DEFINE_NIC_PROPERTIES(E1000State, conf),
DEFINE_PROP_BIT("extra_mac_registers", E1000State,
compat_flags, E1000_FLAG_MAC_BIT, true),
DEFINE_PROP_BIT("migrate_tso_props", E1000State, DEFINE_PROP_BIT("migrate_tso_props", E1000State,
compat_flags, E1000_FLAG_TSO_BIT, true), compat_flags, E1000_FLAG_TSO_BIT, true),
DEFINE_PROP_BIT("init-vet", E1000State, DEFINE_PROP_BIT("init-vet", E1000State,

44
hw/net/vmxnet3.c
View file

@ -41,19 +41,9 @@
#define PCI_DEVICE_ID_VMWARE_VMXNET3_REVISION 0x1 #define PCI_DEVICE_ID_VMWARE_VMXNET3_REVISION 0x1
#define VMXNET3_MSIX_BAR_SIZE 0x2000 #define VMXNET3_MSIX_BAR_SIZE 0x2000
/* Compatibility flags for migration */
#define VMXNET3_COMPAT_FLAG_OLD_MSI_OFFSETS_BIT 0
#define VMXNET3_COMPAT_FLAG_OLD_MSI_OFFSETS \
(1 << VMXNET3_COMPAT_FLAG_OLD_MSI_OFFSETS_BIT)
#define VMXNET3_COMPAT_FLAG_DISABLE_PCIE_BIT 1
#define VMXNET3_COMPAT_FLAG_DISABLE_PCIE \
(1 << VMXNET3_COMPAT_FLAG_DISABLE_PCIE_BIT)
#define VMXNET3_EXP_EP_OFFSET (0x48) #define VMXNET3_EXP_EP_OFFSET (0x48)
#define VMXNET3_MSI_OFFSET(s) \ #define VMXNET3_MSI_OFFSET (0x84)
((s)->compat_flags & VMXNET3_COMPAT_FLAG_OLD_MSI_OFFSETS ? 0x50 : 0x84) #define VMXNET3_MSIX_OFFSET (0x9c)
#define VMXNET3_MSIX_OFFSET(s) \
((s)->compat_flags & VMXNET3_COMPAT_FLAG_OLD_MSI_OFFSETS ? 0 : 0x9c)
#define VMXNET3_DSN_OFFSET (0x100) #define VMXNET3_DSN_OFFSET (0x100)
#define VMXNET3_BAR0_IDX (0) #define VMXNET3_BAR0_IDX (0)
@ -61,8 +51,7 @@
#define VMXNET3_MSIX_BAR_IDX (2) #define VMXNET3_MSIX_BAR_IDX (2)
#define VMXNET3_OFF_MSIX_TABLE (0x000) #define VMXNET3_OFF_MSIX_TABLE (0x000)
#define VMXNET3_OFF_MSIX_PBA(s) \ #define VMXNET3_OFF_MSIX_PBA (0x1000)
((s)->compat_flags & VMXNET3_COMPAT_FLAG_OLD_MSI_OFFSETS ? 0x800 : 0x1000)
/* Link speed in Mbps should be shifted by 16 */ /* Link speed in Mbps should be shifted by 16 */
#define VMXNET3_LINK_SPEED (1000 << 16) #define VMXNET3_LINK_SPEED (1000 << 16)
@ -2122,8 +2111,8 @@ vmxnet3_init_msix(VMXNET3State *s)
&s->msix_bar, &s->msix_bar,
VMXNET3_MSIX_BAR_IDX, VMXNET3_OFF_MSIX_TABLE, VMXNET3_MSIX_BAR_IDX, VMXNET3_OFF_MSIX_TABLE,
&s->msix_bar, &s->msix_bar,
VMXNET3_MSIX_BAR_IDX, VMXNET3_OFF_MSIX_PBA(s), VMXNET3_MSIX_BAR_IDX, VMXNET3_OFF_MSIX_PBA,
VMXNET3_MSIX_OFFSET(s), NULL); VMXNET3_MSIX_OFFSET, NULL);
if (0 > res) { if (0 > res) {
VMW_WRPRN("Failed to initialize MSI-X, error %d", res); VMW_WRPRN("Failed to initialize MSI-X, error %d", res);
@ -2221,7 +2210,7 @@ static void vmxnet3_pci_realize(PCIDevice *pci_dev, Error **errp)
/* Interrupt pin A */ /* Interrupt pin A */
pci_dev->config[PCI_INTERRUPT_PIN] = 0x01; pci_dev->config[PCI_INTERRUPT_PIN] = 0x01;
ret = msi_init(pci_dev, VMXNET3_MSI_OFFSET(s), VMXNET3_MAX_NMSIX_INTRS, ret = msi_init(pci_dev, VMXNET3_MSI_OFFSET, VMXNET3_MAX_NMSIX_INTRS,
VMXNET3_USE_64BIT, VMXNET3_PER_VECTOR_MASK, NULL); VMXNET3_USE_64BIT, VMXNET3_PER_VECTOR_MASK, NULL);
/* Any error other than -ENOTSUP(board's MSI support is broken) /* Any error other than -ENOTSUP(board's MSI support is broken)
* is a programming error. Fall back to INTx silently on -ENOTSUP */ * is a programming error. Fall back to INTx silently on -ENOTSUP */
@ -2249,6 +2238,7 @@ static void vmxnet3_instance_init(Object *obj)
device_add_bootindex_property(obj, &s->conf.bootindex, device_add_bootindex_property(obj, &s->conf.bootindex,
"bootindex", "/ethernet-phy@0", "bootindex", "/ethernet-phy@0",
DEVICE(obj)); DEVICE(obj));
PCI_DEVICE(obj)->cap_present |= QEMU_PCI_CAP_EXPRESS;
} }
static void vmxnet3_pci_uninit(PCIDevice *pci_dev) static void vmxnet3_pci_uninit(PCIDevice *pci_dev)
@ -2472,30 +2462,12 @@ static const VMStateDescription vmstate_vmxnet3 = {
static const Property vmxnet3_properties[] = { static const Property vmxnet3_properties[] = {
DEFINE_NIC_PROPERTIES(VMXNET3State, conf), DEFINE_NIC_PROPERTIES(VMXNET3State, conf),
DEFINE_PROP_BIT("x-old-msi-offsets", VMXNET3State, compat_flags,
VMXNET3_COMPAT_FLAG_OLD_MSI_OFFSETS_BIT, false),
DEFINE_PROP_BIT("x-disable-pcie", VMXNET3State, compat_flags,
VMXNET3_COMPAT_FLAG_DISABLE_PCIE_BIT, false),
}; };
static void vmxnet3_realize(DeviceState *qdev, Error **errp)
{
VMXNET3Class *vc = VMXNET3_DEVICE_GET_CLASS(qdev);
PCIDevice *pci_dev = PCI_DEVICE(qdev);
VMXNET3State *s = VMXNET3(qdev);
if (!(s->compat_flags & VMXNET3_COMPAT_FLAG_DISABLE_PCIE)) {
pci_dev->cap_present |= QEMU_PCI_CAP_EXPRESS;
}
vc->parent_dc_realize(qdev, errp);
}
static void vmxnet3_class_init(ObjectClass *class, const void *data) static void vmxnet3_class_init(ObjectClass *class, const void *data)
{ {
DeviceClass *dc = DEVICE_CLASS(class); DeviceClass *dc = DEVICE_CLASS(class);
PCIDeviceClass *c = PCI_DEVICE_CLASS(class); PCIDeviceClass *c = PCI_DEVICE_CLASS(class);
VMXNET3Class *vc = VMXNET3_DEVICE_CLASS(class);
c->realize = vmxnet3_pci_realize; c->realize = vmxnet3_pci_realize;
c->exit = vmxnet3_pci_uninit; c->exit = vmxnet3_pci_uninit;
@ -2506,8 +2478,6 @@ static void vmxnet3_class_init(ObjectClass *class, const void *data)
c->class_id = PCI_CLASS_NETWORK_ETHERNET; c->class_id = PCI_CLASS_NETWORK_ETHERNET;
c->subsystem_vendor_id = PCI_VENDOR_ID_VMWARE; c->subsystem_vendor_id = PCI_VENDOR_ID_VMWARE;
c->subsystem_id = PCI_DEVICE_ID_VMWARE_VMXNET3; c->subsystem_id = PCI_DEVICE_ID_VMWARE_VMXNET3;
device_class_set_parent_realize(dc, vmxnet3_realize,
&vc->parent_dc_realize);
dc->desc = "VMWare Paravirtualized Ethernet v3"; dc->desc = "VMWare Paravirtualized Ethernet v3";
device_class_set_legacy_reset(dc, vmxnet3_qdev_reset); device_class_set_legacy_reset(dc, vmxnet3_qdev_reset);
dc->vmsd = &vmstate_vmxnet3; dc->vmsd = &vmstate_vmxnet3;

110
hw/nvram/fw_cfg.c
View file

@ -817,62 +817,6 @@ void fw_cfg_modify_i64(FWCfgState *s, uint16_t key, uint64_t value)
g_free(old); g_free(old);
} }
void fw_cfg_set_order_override(FWCfgState *s, int order)
{
assert(s->fw_cfg_order_override == 0);
s->fw_cfg_order_override = order;
}
void fw_cfg_reset_order_override(FWCfgState *s)
{
assert(s->fw_cfg_order_override != 0);
s->fw_cfg_order_override = 0;
}
/*
* This is the legacy order list. For legacy systems, files are in
* the fw_cfg in the order defined below, by the "order" value. Note
* that some entries (VGA ROMs, NIC option ROMS, etc.) go into a
* specific area, but there may be more than one and they occur in the
* order that the user specifies them on the command line. Those are
* handled in a special manner, using the order override above.
*
* For non-legacy, the files are sorted by filename to avoid this kind
* of complexity in the future.
*
* This is only for x86, other arches don't implement versioning so
* they won't set legacy mode.
*/
static struct {
const char *name;
int order;
} fw_cfg_order[] = {
{ "etc/boot-menu-wait", 10 },
{ "bootsplash.jpg", 11 },
{ "bootsplash.bmp", 12 },
{ "etc/boot-fail-wait", 15 },
{ "etc/smbios/smbios-tables", 20 },
{ "etc/smbios/smbios-anchor", 30 },
{ "etc/e820", 40 },
{ "etc/reserved-memory-end", 50 },
{ "genroms/kvmvapic.bin", 55 },
{ "genroms/linuxboot.bin", 60 },
{ }, /* VGA ROMs from pc_vga_init come here, 70. */
{ }, /* NIC option ROMs from pc_nic_init come here, 80. */
{ "etc/system-states", 90 },
{ }, /* User ROMs come here, 100. */
{ }, /* Device FW comes here, 110. */
{ "etc/extra-pci-roots", 120 },
{ "etc/acpi/tables", 130 },
{ "etc/table-loader", 140 },
{ "etc/tpm/log", 150 },
{ "etc/acpi/rsdp", 160 },
{ "bootorder", 170 },
{ "etc/msr_feature_control", 180 },
#define FW_CFG_ORDER_OVERRIDE_LAST 200
};
/* /*
* Any sub-page size update to these table MRs will be lost during migration, * Any sub-page size update to these table MRs will be lost during migration,
* as we use aligned size in ram_load_precopy() -> qemu_ram_resize() path. * as we use aligned size in ram_load_precopy() -> qemu_ram_resize() path.
@ -890,29 +834,6 @@ static void fw_cfg_acpi_mr_save(FWCfgState *s, const char *filename, size_t len)
} }
} }
static int get_fw_cfg_order(FWCfgState *s, const char *name)
{
int i;
if (s->fw_cfg_order_override > 0) {
return s->fw_cfg_order_override;
}
for (i = 0; i < ARRAY_SIZE(fw_cfg_order); i++) {
if (fw_cfg_order[i].name == NULL) {
continue;
}
if (strcmp(name, fw_cfg_order[i].name) == 0) {
return fw_cfg_order[i].order;
}
}
/* Stick unknown stuff at the end. */
warn_report("Unknown firmware file in legacy mode: %s", name);
return FW_CFG_ORDER_OVERRIDE_LAST;
}
void fw_cfg_add_file_callback(FWCfgState *s, const char *filename, void fw_cfg_add_file_callback(FWCfgState *s, const char *filename,
FWCfgCallback select_cb, FWCfgCallback select_cb,
FWCfgWriteCallback write_cb, FWCfgWriteCallback write_cb,
@ -921,7 +842,6 @@ void fw_cfg_add_file_callback(FWCfgState *s, const char *filename,
{ {
int i, index, count; int i, index, count;
size_t dsize; size_t dsize;
MachineClass *mc = MACHINE_GET_CLASS(qdev_get_machine());
int order = 0; int order = 0;
if (!s->files) { if (!s->files) {
@ -933,22 +853,11 @@ void fw_cfg_add_file_callback(FWCfgState *s, const char *filename,
count = be32_to_cpu(s->files->count); count = be32_to_cpu(s->files->count);
assert(count < fw_cfg_file_slots(s)); assert(count < fw_cfg_file_slots(s));
/* Find the insertion point. */ /* Find the insertion point, sorting by file name. */
if (mc->legacy_fw_cfg_order) { for (index = count;
/* index > 0 && strcmp(filename, s->files->f[index - 1].name) < 0;
* Sort by order. For files with the same order, we keep them index--)
* in the sequence in which they were added. ;
*/
order = get_fw_cfg_order(s, filename);
for (index = count;
index > 0 && order < s->entry_order[index - 1];
index--);
} else {
/* Sort by file name. */
for (index = count;
index > 0 && strcmp(filename, s->files->f[index - 1].name) < 0;
index--);
}
/* /*
* Move all the entries from the index point and after down one * Move all the entries from the index point and after down one
@ -1058,7 +967,6 @@ bool fw_cfg_add_file_from_generator(FWCfgState *s,
static void fw_cfg_machine_reset(void *opaque) static void fw_cfg_machine_reset(void *opaque)
{ {
MachineClass *mc = MACHINE_GET_CLASS(qdev_get_machine());
FWCfgState *s = opaque; FWCfgState *s = opaque;
void *ptr; void *ptr;
size_t len; size_t len;
@ -1068,11 +976,9 @@ static void fw_cfg_machine_reset(void *opaque)
ptr = fw_cfg_modify_file(s, "bootorder", (uint8_t *)buf, len); ptr = fw_cfg_modify_file(s, "bootorder", (uint8_t *)buf, len);
g_free(ptr); g_free(ptr);
if (!mc->legacy_fw_cfg_order) { buf = get_boot_devices_lchs_list(&len);
buf = get_boot_devices_lchs_list(&len); ptr = fw_cfg_modify_file(s, "bios-geometry", (uint8_t *)buf, len);
ptr = fw_cfg_modify_file(s, "bios-geometry", (uint8_t *)buf, len); g_free(ptr);
g_free(ptr);
}
} }
static void fw_cfg_machine_ready(struct Notifier *n, void *data) static void fw_cfg_machine_ready(struct Notifier *n, void *data)

67
hw/scsi/vmw_pvscsi.c
View file

@ -68,18 +68,7 @@ struct PVSCSIClass {
OBJECT_DECLARE_TYPE(PVSCSIState, PVSCSIClass, PVSCSI) OBJECT_DECLARE_TYPE(PVSCSIState, PVSCSIClass, PVSCSI)
/* Compatibility flags for migration */ #define PVSCSI_MSI_OFFSET (0x7c)
#define PVSCSI_COMPAT_OLD_PCI_CONFIGURATION_BIT 0
#define PVSCSI_COMPAT_OLD_PCI_CONFIGURATION \
(1 << PVSCSI_COMPAT_OLD_PCI_CONFIGURATION_BIT)
#define PVSCSI_COMPAT_DISABLE_PCIE_BIT 1
#define PVSCSI_COMPAT_DISABLE_PCIE \
(1 << PVSCSI_COMPAT_DISABLE_PCIE_BIT)
#define PVSCSI_USE_OLD_PCI_CONFIGURATION(s) \
((s)->compat_flags & PVSCSI_COMPAT_OLD_PCI_CONFIGURATION)
#define PVSCSI_MSI_OFFSET(s) \
(PVSCSI_USE_OLD_PCI_CONFIGURATION(s) ? 0x50 : 0x7c)
#define PVSCSI_EXP_EP_OFFSET (0x40) #define PVSCSI_EXP_EP_OFFSET (0x40)
typedef struct PVSCSIRingInfo { typedef struct PVSCSIRingInfo {
@ -129,8 +118,6 @@ struct PVSCSIState {
uint8_t msi_used; /* For migration compatibility */ uint8_t msi_used; /* For migration compatibility */
PVSCSIRingInfo rings; /* Data transfer rings manager */ PVSCSIRingInfo rings; /* Data transfer rings manager */
uint32_t resetting; /* Reset in progress */ uint32_t resetting; /* Reset in progress */
uint32_t compat_flags;
}; };
typedef struct PVSCSIRequest { typedef struct PVSCSIRequest {
@ -1110,7 +1097,7 @@ pvscsi_init_msi(PVSCSIState *s)
int res; int res;
PCIDevice *d = PCI_DEVICE(s); PCIDevice *d = PCI_DEVICE(s);
res = msi_init(d, PVSCSI_MSI_OFFSET(s), PVSCSI_MSIX_NUM_VECTORS, res = msi_init(d, PVSCSI_MSI_OFFSET, PVSCSI_MSIX_NUM_VECTORS,
PVSCSI_USE_64BIT, PVSCSI_PER_VECTOR_MASK, NULL); PVSCSI_USE_64BIT, PVSCSI_PER_VECTOR_MASK, NULL);
if (res < 0) { if (res < 0) {
trace_pvscsi_init_msi_fail(res); trace_pvscsi_init_msi_fail(res);
@ -1158,15 +1145,11 @@ pvscsi_realizefn(PCIDevice *pci_dev, Error **errp)
trace_pvscsi_state("init"); trace_pvscsi_state("init");
/* PCI subsystem ID, subsystem vendor ID, revision */ /* PCI subsystem ID, subsystem vendor ID, revision */
if (PVSCSI_USE_OLD_PCI_CONFIGURATION(s)) { pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID,
pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID, 0x1000); PCI_VENDOR_ID_VMWARE);
} else { pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID,
pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID, PCI_DEVICE_ID_VMWARE_PVSCSI);
PCI_VENDOR_ID_VMWARE); pci_config_set_revision(pci_dev->config, 0x2);
pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID,
PCI_DEVICE_ID_VMWARE_PVSCSI);
pci_config_set_revision(pci_dev->config, 0x2);
}
/* PCI latency timer = 255 */ /* PCI latency timer = 255 */
pci_dev->config[PCI_LATENCY_TIMER] = 0xff; pci_dev->config[PCI_LATENCY_TIMER] = 0xff;
@ -1234,21 +1217,8 @@ pvscsi_post_load(void *opaque, int version_id)
return 0; return 0;
} }
static bool pvscsi_vmstate_need_pcie_device(void *opaque)
{
PVSCSIState *s = PVSCSI(opaque);
return !(s->compat_flags & PVSCSI_COMPAT_DISABLE_PCIE);
}
static bool pvscsi_vmstate_test_pci_device(void *opaque, int version_id)
{
return !pvscsi_vmstate_need_pcie_device(opaque);
}
static const VMStateDescription vmstate_pvscsi_pcie_device = { static const VMStateDescription vmstate_pvscsi_pcie_device = {
.name = "pvscsi/pcie", .name = "pvscsi/pcie",
.needed = pvscsi_vmstate_need_pcie_device,
.fields = (const VMStateField[]) { .fields = (const VMStateField[]) {
VMSTATE_PCI_DEVICE(parent_obj, PVSCSIState), VMSTATE_PCI_DEVICE(parent_obj, PVSCSIState),
VMSTATE_END_OF_LIST() VMSTATE_END_OF_LIST()
@ -1262,9 +1232,6 @@ static const VMStateDescription vmstate_pvscsi = {
.pre_save = pvscsi_pre_save, .pre_save = pvscsi_pre_save,
.post_load = pvscsi_post_load, .post_load = pvscsi_post_load,
.fields = (const VMStateField[]) { .fields = (const VMStateField[]) {
VMSTATE_STRUCT_TEST(parent_obj, PVSCSIState,
pvscsi_vmstate_test_pci_device, 0,
vmstate_pci_device, PCIDevice),
VMSTATE_UINT8(msi_used, PVSCSIState), VMSTATE_UINT8(msi_used, PVSCSIState),
VMSTATE_UINT32(resetting, PVSCSIState), VMSTATE_UINT32(resetting, PVSCSIState),
VMSTATE_UINT64(reg_interrupt_status, PVSCSIState), VMSTATE_UINT64(reg_interrupt_status, PVSCSIState),
@ -1298,30 +1265,17 @@ static const VMStateDescription vmstate_pvscsi = {
static const Property pvscsi_properties[] = { static const Property pvscsi_properties[] = {
DEFINE_PROP_UINT8("use_msg", PVSCSIState, use_msg, 1), DEFINE_PROP_UINT8("use_msg", PVSCSIState, use_msg, 1),
DEFINE_PROP_BIT("x-old-pci-configuration", PVSCSIState, compat_flags,
PVSCSI_COMPAT_OLD_PCI_CONFIGURATION_BIT, false),
DEFINE_PROP_BIT("x-disable-pcie", PVSCSIState, compat_flags,
PVSCSI_COMPAT_DISABLE_PCIE_BIT, false),
}; };
static void pvscsi_realize(DeviceState *qdev, Error **errp) static void pvscsi_instance_init(Object *obj)
{ {
PVSCSIClass *pvs_c = PVSCSI_GET_CLASS(qdev); PCI_DEVICE(obj)->cap_present |= QEMU_PCI_CAP_EXPRESS;
PCIDevice *pci_dev = PCI_DEVICE(qdev);
PVSCSIState *s = PVSCSI(qdev);
if (!(s->compat_flags & PVSCSI_COMPAT_DISABLE_PCIE)) {
pci_dev->cap_present |= QEMU_PCI_CAP_EXPRESS;
}
pvs_c->parent_dc_realize(qdev, errp);
} }
static void pvscsi_class_init(ObjectClass *klass, const void *data) static void pvscsi_class_init(ObjectClass *klass, const void *data)
{ {
DeviceClass *dc = DEVICE_CLASS(klass); DeviceClass *dc = DEVICE_CLASS(klass);
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
PVSCSIClass *pvs_k = PVSCSI_CLASS(klass);
HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(klass); HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(klass);
k->realize = pvscsi_realizefn; k->realize = pvscsi_realizefn;
@ -1330,8 +1284,6 @@ static void pvscsi_class_init(ObjectClass *klass, const void *data)
k->device_id = PCI_DEVICE_ID_VMWARE_PVSCSI; k->device_id = PCI_DEVICE_ID_VMWARE_PVSCSI;
k->class_id = PCI_CLASS_STORAGE_SCSI; k->class_id = PCI_CLASS_STORAGE_SCSI;
k->subsystem_id = 0x1000; k->subsystem_id = 0x1000;
device_class_set_parent_realize(dc, pvscsi_realize,
&pvs_k->parent_dc_realize);
device_class_set_legacy_reset(dc, pvscsi_reset); device_class_set_legacy_reset(dc, pvscsi_reset);
dc->vmsd = &vmstate_pvscsi; dc->vmsd = &vmstate_pvscsi;
device_class_set_props(dc, pvscsi_properties); device_class_set_props(dc, pvscsi_properties);
@ -1346,6 +1298,7 @@ static const TypeInfo pvscsi_info = {
.class_size = sizeof(PVSCSIClass), .class_size = sizeof(PVSCSIClass),
.instance_size = sizeof(PVSCSIState), .instance_size = sizeof(PVSCSIState),
.class_init = pvscsi_class_init, .class_init = pvscsi_class_init,
.instance_init = pvscsi_instance_init,
.interfaces = (const InterfaceInfo[]) { .interfaces = (const InterfaceInfo[]) {
{ TYPE_HOTPLUG_HANDLER }, { TYPE_HOTPLUG_HANDLER },
{ INTERFACE_PCIE_DEVICE }, { INTERFACE_PCIE_DEVICE },

11
hw/virtio/virtio-pci.c
View file

@ -146,9 +146,7 @@ static const VMStateDescription vmstate_virtio_pci = {
static bool virtio_pci_has_extra_state(DeviceState *d) static bool virtio_pci_has_extra_state(DeviceState *d)
{ {
VirtIOPCIProxy *proxy = to_virtio_pci_proxy(d); return true;
return proxy->flags & VIRTIO_PCI_FLAG_MIGRATE_EXTRA;
} }
static void virtio_pci_save_extra_state(DeviceState *d, QEMUFile *f) static void virtio_pci_save_extra_state(DeviceState *d, QEMUFile *f)
@ -2363,12 +2361,8 @@ static void virtio_pci_bus_reset_hold(Object *obj, ResetType type)
static const Property virtio_pci_properties[] = { static const Property virtio_pci_properties[] = {
DEFINE_PROP_BIT("virtio-pci-bus-master-bug-migration", VirtIOPCIProxy, flags, DEFINE_PROP_BIT("virtio-pci-bus-master-bug-migration", VirtIOPCIProxy, flags,
VIRTIO_PCI_FLAG_BUS_MASTER_BUG_MIGRATION_BIT, false), VIRTIO_PCI_FLAG_BUS_MASTER_BUG_MIGRATION_BIT, false),
DEFINE_PROP_BIT("migrate-extra", VirtIOPCIProxy, flags,
VIRTIO_PCI_FLAG_MIGRATE_EXTRA_BIT, true),
DEFINE_PROP_BIT("modern-pio-notify", VirtIOPCIProxy, flags, DEFINE_PROP_BIT("modern-pio-notify", VirtIOPCIProxy, flags,
VIRTIO_PCI_FLAG_MODERN_PIO_NOTIFY_BIT, false), VIRTIO_PCI_FLAG_MODERN_PIO_NOTIFY_BIT, false),
DEFINE_PROP_BIT("x-disable-pcie", VirtIOPCIProxy, flags,
VIRTIO_PCI_FLAG_DISABLE_PCIE_BIT, false),
DEFINE_PROP_BIT("page-per-vq", VirtIOPCIProxy, flags, DEFINE_PROP_BIT("page-per-vq", VirtIOPCIProxy, flags,
VIRTIO_PCI_FLAG_PAGE_PER_VQ_BIT, false), VIRTIO_PCI_FLAG_PAGE_PER_VQ_BIT, false),
DEFINE_PROP_BOOL("x-ignore-backend-features", VirtIOPCIProxy, DEFINE_PROP_BOOL("x-ignore-backend-features", VirtIOPCIProxy,
@ -2397,8 +2391,7 @@ static void virtio_pci_dc_realize(DeviceState *qdev, Error **errp)
VirtIOPCIProxy *proxy = VIRTIO_PCI(qdev); VirtIOPCIProxy *proxy = VIRTIO_PCI(qdev);
PCIDevice *pci_dev = &proxy->pci_dev; PCIDevice *pci_dev = &proxy->pci_dev;
if (!(proxy->flags & VIRTIO_PCI_FLAG_DISABLE_PCIE) && if (virtio_pci_modern(proxy)) {
virtio_pci_modern(proxy)) {
pci_dev->cap_present |= QEMU_PCI_CAP_EXPRESS; pci_dev->cap_present |= QEMU_PCI_CAP_EXPRESS;
} }

9
include/hw/boards.h
View file

@ -286,8 +286,7 @@ struct MachineClass {
no_parallel:1, no_parallel:1,
no_floppy:1, no_floppy:1,
no_cdrom:1, no_cdrom:1,
pci_allow_0_address:1, pci_allow_0_address:1;
legacy_fw_cfg_order:1;
bool auto_create_sdcard; bool auto_create_sdcard;
bool is_default; bool is_default;
const char *default_machine_opts; const char *default_machine_opts;
@ -863,10 +862,4 @@ extern const size_t hw_compat_2_7_len;
extern GlobalProperty hw_compat_2_6[]; extern GlobalProperty hw_compat_2_6[];
extern const size_t hw_compat_2_6_len; extern const size_t hw_compat_2_6_len;
extern GlobalProperty hw_compat_2_5[];
extern const size_t hw_compat_2_5_len;
extern GlobalProperty hw_compat_2_4[];
extern const size_t hw_compat_2_4_len;
#endif #endif

7
include/hw/i386/pc.h
View file

@ -107,7 +107,6 @@ struct PCMachineClass {
/* RAM / address space compat: */ /* RAM / address space compat: */
bool gigabyte_align; bool gigabyte_align;
bool has_reserved_memory; bool has_reserved_memory;
bool broken_reserved_end;
bool enforce_amd_1tb_hole; bool enforce_amd_1tb_hole;
bool isa_bios_alias; bool isa_bios_alias;
@ -299,12 +298,6 @@ extern const size_t pc_compat_2_7_len;
extern GlobalProperty pc_compat_2_6[]; extern GlobalProperty pc_compat_2_6[];
extern const size_t pc_compat_2_6_len; extern const size_t pc_compat_2_6_len;
extern GlobalProperty pc_compat_2_5[];
extern const size_t pc_compat_2_5_len;
extern GlobalProperty pc_compat_2_4[];
extern const size_t pc_compat_2_4_len;
#define DEFINE_PC_MACHINE(suffix, namestr, initfn, optsfn) \ #define DEFINE_PC_MACHINE(suffix, namestr, initfn, optsfn) \
static void pc_machine_##suffix##_class_init(ObjectClass *oc, \ static void pc_machine_##suffix##_class_init(ObjectClass *oc, \
const void *data) \ const void *data) \

5
include/hw/i386/x86.h
View file

@ -27,13 +27,8 @@
#include "qom/object.h" #include "qom/object.h"
struct X86MachineClass { struct X86MachineClass {
/*< private >*/
MachineClass parent; MachineClass parent;
/*< public >*/
/* TSC rate migration: */
bool save_tsc_khz;
/* use DMA capable linuxboot option rom */ /* use DMA capable linuxboot option rom */
bool fwcfg_dma_enabled; bool fwcfg_dma_enabled;
/* CPU and apic information: */ /* CPU and apic information: */

2
include/hw/loader.h
View file

@ -270,8 +270,6 @@ int rom_add_elf_program(const char *name, GMappedFile *mapped_file, void *data,
AddressSpace *as); AddressSpace *as);
int rom_check_and_register_reset(void); int rom_check_and_register_reset(void);
void rom_set_fw(FWCfgState *f); void rom_set_fw(FWCfgState *f);
void rom_set_order_override(int order);
void rom_reset_order_override(void);
/** /**
* rom_transaction_begin: * rom_transaction_begin:

10
include/hw/nvram/fw_cfg.h
View file

@ -42,14 +42,6 @@ struct FWCfgDataGeneratorClass {
typedef struct fw_cfg_file FWCfgFile; typedef struct fw_cfg_file FWCfgFile;
#define FW_CFG_ORDER_OVERRIDE_VGA 70
#define FW_CFG_ORDER_OVERRIDE_NIC 80
#define FW_CFG_ORDER_OVERRIDE_USER 100
#define FW_CFG_ORDER_OVERRIDE_DEVICE 110
void fw_cfg_set_order_override(FWCfgState *fw_cfg, int order);
void fw_cfg_reset_order_override(FWCfgState *fw_cfg);
typedef struct FWCfgFiles { typedef struct FWCfgFiles {
uint32_t count; uint32_t count;
FWCfgFile f[]; FWCfgFile f[];
@ -75,8 +67,6 @@ struct FWCfgState {
uint32_t cur_offset; uint32_t cur_offset;
Notifier machine_ready; Notifier machine_ready;
int fw_cfg_order_override;
bool dma_enabled; bool dma_enabled;
dma_addr_t dma_addr; dma_addr_t dma_addr;
AddressSpace *dma_as; AddressSpace *dma_as;

8
include/hw/virtio/virtio-pci.h
View file

@ -32,9 +32,7 @@ DECLARE_OBJ_CHECKERS(VirtioPCIBusState, VirtioPCIBusClass,
enum { enum {
VIRTIO_PCI_FLAG_BUS_MASTER_BUG_MIGRATION_BIT, VIRTIO_PCI_FLAG_BUS_MASTER_BUG_MIGRATION_BIT,
VIRTIO_PCI_FLAG_USE_IOEVENTFD_BIT, VIRTIO_PCI_FLAG_USE_IOEVENTFD_BIT,
VIRTIO_PCI_FLAG_MIGRATE_EXTRA_BIT,
VIRTIO_PCI_FLAG_MODERN_PIO_NOTIFY_BIT, VIRTIO_PCI_FLAG_MODERN_PIO_NOTIFY_BIT,
VIRTIO_PCI_FLAG_DISABLE_PCIE_BIT,
VIRTIO_PCI_FLAG_PAGE_PER_VQ_BIT, VIRTIO_PCI_FLAG_PAGE_PER_VQ_BIT,
VIRTIO_PCI_FLAG_ATS_BIT, VIRTIO_PCI_FLAG_ATS_BIT,
VIRTIO_PCI_FLAG_INIT_DEVERR_BIT, VIRTIO_PCI_FLAG_INIT_DEVERR_BIT,
@ -54,12 +52,6 @@ enum {
* vcpu thread using ioeventfd for some devices. */ * vcpu thread using ioeventfd for some devices. */
#define VIRTIO_PCI_FLAG_USE_IOEVENTFD (1 << VIRTIO_PCI_FLAG_USE_IOEVENTFD_BIT) #define VIRTIO_PCI_FLAG_USE_IOEVENTFD (1 << VIRTIO_PCI_FLAG_USE_IOEVENTFD_BIT)
/* virtio version flags */
#define VIRTIO_PCI_FLAG_DISABLE_PCIE (1 << VIRTIO_PCI_FLAG_DISABLE_PCIE_BIT)
/* migrate extra state */
#define VIRTIO_PCI_FLAG_MIGRATE_EXTRA (1 << VIRTIO_PCI_FLAG_MIGRATE_EXTRA_BIT)
/* have pio notification for modern device ? */ /* have pio notification for modern device ? */
#define VIRTIO_PCI_FLAG_MODERN_PIO_NOTIFY \ #define VIRTIO_PCI_FLAG_MODERN_PIO_NOTIFY \
(1 << VIRTIO_PCI_FLAG_MODERN_PIO_NOTIFY_BIT) (1 << VIRTIO_PCI_FLAG_MODERN_PIO_NOTIFY_BIT)

5
system/vl.c
View file

@ -1192,10 +1192,7 @@ static int parse_fw_cfg(void *opaque, QemuOpts *opts, Error **errp)
return -1; return -1;
} }
} }
/* For legacy, keep user files in a specific global order. */
fw_cfg_set_order_override(fw_cfg, FW_CFG_ORDER_OVERRIDE_USER);
fw_cfg_add_file(fw_cfg, name, buf, size); fw_cfg_add_file(fw_cfg, name, buf, size);
fw_cfg_reset_order_override(fw_cfg);
return 0; return 0;
} }
@ -2745,7 +2742,6 @@ static void qemu_create_cli_devices(void)
} }
/* init generic devices */ /* init generic devices */
rom_set_order_override(FW_CFG_ORDER_OVERRIDE_DEVICE);
qemu_opts_foreach(qemu_find_opts("device"), qemu_opts_foreach(qemu_find_opts("device"),
device_init_func, NULL, &error_fatal); device_init_func, NULL, &error_fatal);
QTAILQ_FOREACH(opt, &device_opts, next) { QTAILQ_FOREACH(opt, &device_opts, next) {
@ -2756,7 +2752,6 @@ static void qemu_create_cli_devices(void)
assert(ret_data == NULL); /* error_fatal aborts */ assert(ret_data == NULL); /* error_fatal aborts */
loc_pop(&opt->loc); loc_pop(&opt->loc);
} }
rom_reset_order_override();
} }
static bool qemu_machine_creation_done(Error **errp) static bool qemu_machine_creation_done(Error **errp)

5
target/i386/machine.c
View file

@ -1060,9 +1060,8 @@ static bool tsc_khz_needed(void *opaque)
{ {
X86CPU *cpu = opaque; X86CPU *cpu = opaque;
CPUX86State *env = &cpu->env; CPUX86State *env = &cpu->env;
MachineClass *mc = MACHINE_GET_CLASS(qdev_get_machine());
X86MachineClass *x86mc = X86_MACHINE_CLASS(mc); return env->tsc_khz;
return env->tsc_khz && x86mc->save_tsc_khz;
} }
static const VMStateDescription vmstate_tsc_khz = { static const VMStateDescription vmstate_tsc_khz = {

63
tests/functional/test_mem_addr_space.py
View file

@ -58,8 +58,8 @@ class MemAddrCheck(QemuSystemTest):
should start fine. should start fine.
""" """
self.ensure_64bit_binary() self.ensure_64bit_binary()
self.vm.add_args('-S', '-machine', 'q35', '-m', self.set_machine('q35')
'512,slots=1,maxmem=59.6G', self.vm.add_args('-S', '-m', '512,slots=1,maxmem=59.6G',
'-cpu', 'pentium,pse36=on', '-display', 'none', '-cpu', 'pentium,pse36=on', '-display', 'none',
'-object', 'memory-backend-ram,id=mem1,size=1G', '-object', 'memory-backend-ram,id=mem1,size=1G',
'-device', 'pc-dimm,id=vm0,memdev=mem1') '-device', 'pc-dimm,id=vm0,memdev=mem1')
@ -76,8 +76,8 @@ class MemAddrCheck(QemuSystemTest):
with pse36 above. with pse36 above.
""" """
self.ensure_64bit_binary() self.ensure_64bit_binary()
self.vm.add_args('-S', '-machine', 'q35', '-m', self.set_machine('q35')
'512,slots=1,maxmem=59.6G', self.vm.add_args('-S', '-m', '512,slots=1,maxmem=59.6G',
'-cpu', 'pentium,pae=on', '-display', 'none', '-cpu', 'pentium,pae=on', '-display', 'none',
'-object', 'memory-backend-ram,id=mem1,size=1G', '-object', 'memory-backend-ram,id=mem1,size=1G',
'-device', 'pc-dimm,id=vm0,memdev=mem1') '-device', 'pc-dimm,id=vm0,memdev=mem1')
@ -93,8 +93,8 @@ class MemAddrCheck(QemuSystemTest):
same options as the failing case above with pse36 cpu feature. same options as the failing case above with pse36 cpu feature.
""" """
self.ensure_64bit_binary() self.ensure_64bit_binary()
self.vm.add_args('-machine', 'q35', '-m', self.set_machine('q35')
'512,slots=1,maxmem=59.5G', self.vm.add_args('-m', '512,slots=1,maxmem=59.5G',
'-cpu', 'pentium,pse36=on', '-display', 'none', '-cpu', 'pentium,pse36=on', '-display', 'none',
'-object', 'memory-backend-ram,id=mem1,size=1G', '-object', 'memory-backend-ram,id=mem1,size=1G',
'-device', 'pc-dimm,id=vm0,memdev=mem1') '-device', 'pc-dimm,id=vm0,memdev=mem1')
@ -111,8 +111,8 @@ class MemAddrCheck(QemuSystemTest):
with the same options as the case above. with the same options as the case above.
""" """
self.ensure_64bit_binary() self.ensure_64bit_binary()
self.vm.add_args('-machine', 'q35', '-m', self.set_machine('q35')
'512,slots=1,maxmem=59.5G', self.vm.add_args('-m', '512,slots=1,maxmem=59.5G',
'-cpu', 'pentium,pae=on', '-display', 'none', '-cpu', 'pentium,pae=on', '-display', 'none',
'-object', 'memory-backend-ram,id=mem1,size=1G', '-object', 'memory-backend-ram,id=mem1,size=1G',
'-device', 'pc-dimm,id=vm0,memdev=mem1') '-device', 'pc-dimm,id=vm0,memdev=mem1')
@ -128,8 +128,8 @@ class MemAddrCheck(QemuSystemTest):
with pse36 ON. with pse36 ON.
""" """
self.ensure_64bit_binary() self.ensure_64bit_binary()
self.vm.add_args('-machine', 'q35', '-m', self.set_machine('q35')
'512,slots=1,maxmem=59.5G', self.vm.add_args('-m', '512,slots=1,maxmem=59.5G',
'-cpu', 'pentium2', '-display', 'none', '-cpu', 'pentium2', '-display', 'none',
'-object', 'memory-backend-ram,id=mem1,size=1G', '-object', 'memory-backend-ram,id=mem1,size=1G',
'-device', 'pc-dimm,id=vm0,memdev=mem1') '-device', 'pc-dimm,id=vm0,memdev=mem1')
@ -148,8 +148,8 @@ class MemAddrCheck(QemuSystemTest):
above 4 GiB due to the PCI hole and simplicity. above 4 GiB due to the PCI hole and simplicity.
""" """
self.ensure_64bit_binary() self.ensure_64bit_binary()
self.vm.add_args('-S', '-machine', 'q35', '-m', self.set_machine('q35')
'512,slots=1,maxmem=4G', self.vm.add_args('-S', '-m', '512,slots=1,maxmem=4G',
'-cpu', 'pentium', '-display', 'none', '-cpu', 'pentium', '-display', 'none',
'-object', 'memory-backend-ram,id=mem1,size=1G', '-object', 'memory-backend-ram,id=mem1,size=1G',
'-device', 'pc-dimm,id=vm0,memdev=mem1') '-device', 'pc-dimm,id=vm0,memdev=mem1')
@ -176,8 +176,8 @@ class MemAddrCheck(QemuSystemTest):
make QEMU fail with the error message. make QEMU fail with the error message.
""" """
self.ensure_64bit_binary() self.ensure_64bit_binary()
self.vm.add_args('-S', '-machine', 'pc-q35-7.0', '-m', self.set_machine('pc-q35-7.0')
'512,slots=1,maxmem=988G', self.vm.add_args('-S', '-m', '512,slots=1,maxmem=988G',
'-display', 'none', '-display', 'none',
'-object', 'memory-backend-ram,id=mem1,size=1G', '-object', 'memory-backend-ram,id=mem1,size=1G',
'-device', 'pc-dimm,id=vm0,memdev=mem1') '-device', 'pc-dimm,id=vm0,memdev=mem1')
@ -197,8 +197,8 @@ class MemAddrCheck(QemuSystemTest):
than 988 GiB). than 988 GiB).
""" """
self.ensure_64bit_binary() self.ensure_64bit_binary()
self.vm.add_args('-S', '-machine', 'pc-q35-7.1', '-m', self.set_machine('pc-q35-7.1')
'512,slots=1,maxmem=976G', self.vm.add_args('-S', '-m', '512,slots=1,maxmem=976G',
'-display', 'none', '-display', 'none',
'-object', 'memory-backend-ram,id=mem1,size=1G', '-object', 'memory-backend-ram,id=mem1,size=1G',
'-device', 'pc-dimm,id=vm0,memdev=mem1') '-device', 'pc-dimm,id=vm0,memdev=mem1')
@ -214,8 +214,8 @@ class MemAddrCheck(QemuSystemTest):
successfully start when maxmem is < 988G. successfully start when maxmem is < 988G.
""" """
self.ensure_64bit_binary() self.ensure_64bit_binary()
self.vm.add_args('-S', '-machine', 'pc-q35-7.0', '-m', self.set_machine('pc-q35-7.0')
'512,slots=1,maxmem=987.5G', self.vm.add_args('-S', '-m', '512,slots=1,maxmem=987.5G',
'-display', 'none', '-display', 'none',
'-object', 'memory-backend-ram,id=mem1,size=1G', '-object', 'memory-backend-ram,id=mem1,size=1G',
'-device', 'pc-dimm,id=vm0,memdev=mem1') '-device', 'pc-dimm,id=vm0,memdev=mem1')
@ -231,8 +231,8 @@ class MemAddrCheck(QemuSystemTest):
successfully start when maxmem is < 976G. successfully start when maxmem is < 976G.
""" """
self.ensure_64bit_binary() self.ensure_64bit_binary()
self.vm.add_args('-S', '-machine', 'pc-q35-7.1', '-m', self.set_machine('pc-q35-7.1')
'512,slots=1,maxmem=975.5G', self.vm.add_args('-S', '-m', '512,slots=1,maxmem=975.5G',
'-display', 'none', '-display', 'none',
'-object', 'memory-backend-ram,id=mem1,size=1G', '-object', 'memory-backend-ram,id=mem1,size=1G',
'-device', 'pc-dimm,id=vm0,memdev=mem1') '-device', 'pc-dimm,id=vm0,memdev=mem1')
@ -249,9 +249,9 @@ class MemAddrCheck(QemuSystemTest):
"above_4G" memory starts at 4G. "above_4G" memory starts at 4G.
""" """
self.ensure_64bit_binary() self.ensure_64bit_binary()
self.set_machine('pc-q35-7.1')
self.vm.add_args('-S', '-cpu', 'Skylake-Server', self.vm.add_args('-S', '-cpu', 'Skylake-Server',
'-machine', 'pc-q35-7.1', '-m', '-m', '512,slots=1,maxmem=976G',
'512,slots=1,maxmem=976G',
'-display', 'none', '-display', 'none',
'-object', 'memory-backend-ram,id=mem1,size=1G', '-object', 'memory-backend-ram,id=mem1,size=1G',
'-device', 'pc-dimm,id=vm0,memdev=mem1') '-device', 'pc-dimm,id=vm0,memdev=mem1')
@ -274,9 +274,9 @@ class MemAddrCheck(QemuSystemTest):
fail to start. fail to start.
""" """
self.ensure_64bit_binary() self.ensure_64bit_binary()
self.set_machine('pc-q35-7.1')
self.vm.add_args('-S', '-cpu', 'EPYC-v4,phys-bits=41', self.vm.add_args('-S', '-cpu', 'EPYC-v4,phys-bits=41',
'-machine', 'pc-q35-7.1', '-m', '-m', '512,slots=1,maxmem=992G',
'512,slots=1,maxmem=992G',
'-display', 'none', '-display', 'none',
'-object', 'memory-backend-ram,id=mem1,size=1G', '-object', 'memory-backend-ram,id=mem1,size=1G',
'-device', 'pc-dimm,id=vm0,memdev=mem1') '-device', 'pc-dimm,id=vm0,memdev=mem1')
@ -293,9 +293,9 @@ class MemAddrCheck(QemuSystemTest):
QEMU should start fine. QEMU should start fine.
""" """
self.ensure_64bit_binary() self.ensure_64bit_binary()
self.set_machine('pc-q35-7.1')
self.vm.add_args('-S', '-cpu', 'EPYC-v4,phys-bits=41', self.vm.add_args('-S', '-cpu', 'EPYC-v4,phys-bits=41',
'-machine', 'pc-q35-7.1', '-m', '-m', '512,slots=1,maxmem=990G',
'512,slots=1,maxmem=990G',
'-display', 'none', '-display', 'none',
'-object', 'memory-backend-ram,id=mem1,size=1G', '-object', 'memory-backend-ram,id=mem1,size=1G',
'-device', 'pc-dimm,id=vm0,memdev=mem1') '-device', 'pc-dimm,id=vm0,memdev=mem1')
@ -314,12 +314,12 @@ class MemAddrCheck(QemuSystemTest):
alignment constraints with 40 bits (1 TiB) of processor physical bits. alignment constraints with 40 bits (1 TiB) of processor physical bits.
""" """
self.ensure_64bit_binary() self.ensure_64bit_binary()
self.set_machine('q35')
self.vm.add_args('-S', '-cpu', 'Skylake-Server,phys-bits=40', self.vm.add_args('-S', '-cpu', 'Skylake-Server,phys-bits=40',
'-machine', 'q35,cxl=on', '-m', '-m', '512,slots=1,maxmem=987G',
'512,slots=1,maxmem=987G',
'-display', 'none', '-display', 'none',
'-device', 'pxb-cxl,bus_nr=12,bus=pcie.0,id=cxl.1', '-device', 'pxb-cxl,bus_nr=12,bus=pcie.0,id=cxl.1',
'-M', 'cxl-fmw.0.targets.0=cxl.1,cxl-fmw.0.size=1G') '-M', 'cxl=on,cxl-fmw.0.targets.0=cxl.1,cxl-fmw.0.size=1G')
self.vm.set_qmp_monitor(enabled=False) self.vm.set_qmp_monitor(enabled=False)
self.vm.launch() self.vm.launch()
self.vm.wait() self.vm.wait()
@ -333,9 +333,10 @@ class MemAddrCheck(QemuSystemTest):
with cxl enabled. with cxl enabled.
""" """
self.ensure_64bit_binary() self.ensure_64bit_binary()
self.set_machine('q35')
self.vm.add_args('-S', '-cpu', 'Skylake-Server,phys-bits=40', self.vm.add_args('-S', '-cpu', 'Skylake-Server,phys-bits=40',
'-machine', 'q35,cxl=on', '-m', '-machine', 'cxl=on',
'512,slots=1,maxmem=987G', '-m', '512,slots=1,maxmem=987G',
'-display', 'none', '-display', 'none',
'-device', 'pxb-cxl,bus_nr=12,bus=pcie.0,id=cxl.1') '-device', 'pxb-cxl,bus_nr=12,bus=pcie.0,id=cxl.1')
self.vm.set_qmp_monitor(enabled=False) self.vm.set_qmp_monitor(enabled=False)

18
tests/functional/test_microblaze_s3adsp1800.py
View file

@ -25,12 +25,14 @@ class MicroblazeMachine(QemuSystemTest):
('http://www.qemu-advent-calendar.org/2023/download/day13.tar.gz'), ('http://www.qemu-advent-calendar.org/2023/download/day13.tar.gz'),
'b9b3d43c5dd79db88ada495cc6e0d1f591153fe41355e925d791fbf44de50c22') 'b9b3d43c5dd79db88ada495cc6e0d1f591153fe41355e925d791fbf44de50c22')
def do_ballerina_be_test(self, machine): def do_ballerina_be_test(self, force_endianness=False):
self.set_machine(machine) self.set_machine('petalogix-s3adsp1800')
self.archive_extract(self.ASSET_IMAGE_BE) self.archive_extract(self.ASSET_IMAGE_BE)
self.vm.set_console() self.vm.set_console()
self.vm.add_args('-kernel', self.vm.add_args('-kernel',
self.scratch_file('day17', 'ballerina.bin')) self.scratch_file('day17', 'ballerina.bin'))
if force_endianness:
self.vm.add_args('-M', 'endianness=big')
self.vm.launch() self.vm.launch()
wait_for_console_pattern(self, 'This architecture does not have ' wait_for_console_pattern(self, 'This architecture does not have '
'kernel memory protection') 'kernel memory protection')
@ -39,12 +41,14 @@ class MicroblazeMachine(QemuSystemTest):
# message, that's why we don't test for a later string here. This # message, that's why we don't test for a later string here. This
# needs some investigation by a microblaze wizard one day... # needs some investigation by a microblaze wizard one day...
def do_xmaton_le_test(self, machine): def do_xmaton_le_test(self, force_endianness=False):
self.require_netdev('user') self.require_netdev('user')
self.set_machine(machine) self.set_machine('petalogix-s3adsp1800')
self.archive_extract(self.ASSET_IMAGE_LE) self.archive_extract(self.ASSET_IMAGE_LE)
self.vm.set_console() self.vm.set_console()
self.vm.add_args('-kernel', self.scratch_file('day13', 'xmaton.bin')) self.vm.add_args('-kernel', self.scratch_file('day13', 'xmaton.bin'))
if force_endianness:
self.vm.add_args('-M', 'endianness=little')
tftproot = self.scratch_file('day13') tftproot = self.scratch_file('day13')
self.vm.add_args('-nic', f'user,tftp={tftproot}') self.vm.add_args('-nic', f'user,tftp={tftproot}')
self.vm.launch() self.vm.launch()
@ -59,9 +63,13 @@ class MicroblazeMachine(QemuSystemTest):
class MicroblazeBigEndianMachine(MicroblazeMachine): class MicroblazeBigEndianMachine(MicroblazeMachine):
ASSET_IMAGE_BE = MicroblazeMachine.ASSET_IMAGE_BE ASSET_IMAGE_BE = MicroblazeMachine.ASSET_IMAGE_BE
ASSET_IMAGE_LE = MicroblazeMachine.ASSET_IMAGE_LE
def test_microblaze_s3adsp1800_legacy_be(self): def test_microblaze_s3adsp1800_legacy_be(self):
self.do_ballerina_be_test('petalogix-s3adsp1800') self.do_ballerina_be_test()
def test_microblaze_s3adsp1800_legacy_le(self):
self.do_xmaton_le_test(force_endianness=True)
if __name__ == '__main__': if __name__ == '__main__':

6
tests/functional/test_microblazeel_s3adsp1800.py
View file

@ -13,9 +13,13 @@ from test_microblaze_s3adsp1800 import MicroblazeMachine
class MicroblazeLittleEndianMachine(MicroblazeMachine): class MicroblazeLittleEndianMachine(MicroblazeMachine):
ASSET_IMAGE_LE = MicroblazeMachine.ASSET_IMAGE_LE ASSET_IMAGE_LE = MicroblazeMachine.ASSET_IMAGE_LE
ASSET_IMAGE_BE = MicroblazeMachine.ASSET_IMAGE_BE
def test_microblaze_s3adsp1800_legacy_le(self): def test_microblaze_s3adsp1800_legacy_le(self):
self.do_xmaton_le_test('petalogix-s3adsp1800') self.do_xmaton_le_test()
def test_microblaze_s3adsp1800_legacy_be(self):
self.do_ballerina_be_test(force_endianness=True)
if __name__ == '__main__': if __name__ == '__main__':

6
tests/functional/test_mips_malta.py
View file

@ -80,10 +80,8 @@ def mips_check_wheezy(test, kernel_path, image_path, kernel_command_line,
exec_command_and_wait_for_pattern(test, 'cat /proc/devices', 'usb') exec_command_and_wait_for_pattern(test, 'cat /proc/devices', 'usb')
exec_command_and_wait_for_pattern(test, 'cat /proc/ioports', exec_command_and_wait_for_pattern(test, 'cat /proc/ioports',
' : piix4_smbus') ' : piix4_smbus')
# lspci for the host bridge does not work on big endian targets: exec_command_and_wait_for_pattern(test, 'lspci -d 11ab:4620',
# https://gitlab.com/qemu-project/qemu/-/issues/2826 'GT-64120')
# exec_command_and_wait_for_pattern(test, 'lspci -d 11ab:4620',
# 'GT-64120')
exec_command_and_wait_for_pattern(test, exec_command_and_wait_for_pattern(test,
'cat /sys/bus/i2c/devices/i2c-0/name', 'cat /sys/bus/i2c/devices/i2c-0/name',
'SMBus PIIX4 adapter') 'SMBus PIIX4 adapter')

1
tests/functional/test_sparc64_tuxrun.py
View file

@ -24,6 +24,7 @@ class TuxRunSparc64Test(TuxRunBaselineTest):
'479c3dc104c82b68be55e2c0c5c38cd473d0b37ad4badccde4775bb88ce34611') '479c3dc104c82b68be55e2c0c5c38cd473d0b37ad4badccde4775bb88ce34611')
def test_sparc64(self): def test_sparc64(self):
self.set_machine('sun4u')
self.root='sda' self.root='sda'
self.wait_for_shutdown=False self.wait_for_shutdown=False
self.common_tuxrun(kernel_asset=self.ASSET_SPARC64_KERNEL, self.common_tuxrun(kernel_asset=self.ASSET_SPARC64_KERNEL,

14
tests/qtest/test-x86-cpuid-compat.c
View file

@ -365,20 +365,6 @@ int main(int argc, char **argv)
"level", 10); "level", 10);
} }
/*
* xlevel doesn't have any feature that triggers auto-level
* code on old machine-types. Just check that the compat code
* is working correctly:
*/
if (qtest_has_machine("pc-i440fx-2.4")) {
add_cpuid_test("x86/cpuid/xlevel-compat/pc-i440fx-2.4/npt-off",
"SandyBridge", NULL, "pc-i440fx-2.4",
"xlevel", 0x80000008);
add_cpuid_test("x86/cpuid/xlevel-compat/pc-i440fx-2.4/npt-on",
"SandyBridge", "svm=on,npt=on", "pc-i440fx-2.4",
"xlevel", 0x80000008);
}
/* Test feature parsing */ /* Test feature parsing */
add_feature_test("x86/cpuid/features/plus", add_feature_test("x86/cpuid/features/plus",
"486", "+arat", "486", "+arat",

4
tests/unit/test-util-sockets.c
View file

@ -341,8 +341,12 @@ static void inet_parse_test_helper(const char *str,
int rc = inet_parse(&addr, str, &error); int rc = inet_parse(&addr, str, &error);
if (success) { if (success) {
if (error) {
error_report_err(error);
}
g_assert_cmpint(rc, ==, 0); g_assert_cmpint(rc, ==, 0);
} else { } else {
error_free(error);
g_assert_cmpint(rc, <, 0); g_assert_cmpint(rc, <, 0);
} }
if (exp_addr != NULL) { if (exp_addr != NULL) {