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target/arm: Test correct register in aa32_pan and aa32_ats1e1 checks

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The isar_feature_aa32_pan and isar_feature_aa32_ats1e1 functions
are supposed to be testing fields in ID_MMFR3; but a cut-and-paste
error meant we were looking at MVFR0 instead.

Fix the functions to look at the right register; this requires
us to move at least id_mmfr3 to the ARMISARegisters struct; we
choose to move all the ID_MMFRn registers for consistency.

Fixes: 3d6ad6bb46
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200214175116.9164-19-peter.maydell@linaro.org
This commit is contained in:
Peter Maydell 2020-02-14 17:51:13 +00:00
parent 62d96ff485
commit 10054016ed
7 changed files with 110 additions and 83 deletions
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8
hw/intc/armv7m_nvic.c
View file

@ -1231,13 +1231,13 @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs)
case 0xd4c: /* AFR0. */ case 0xd4c: /* AFR0. */
return cpu->id_afr0; return cpu->id_afr0;
case 0xd50: /* MMFR0. */ case 0xd50: /* MMFR0. */
return cpu->id_mmfr0; return cpu->isar.id_mmfr0;
case 0xd54: /* MMFR1. */ case 0xd54: /* MMFR1. */
return cpu->id_mmfr1; return cpu->isar.id_mmfr1;
case 0xd58: /* MMFR2. */ case 0xd58: /* MMFR2. */
return cpu->id_mmfr2; return cpu->isar.id_mmfr2;
case 0xd5c: /* MMFR3. */ case 0xd5c: /* MMFR3. */
return cpu->id_mmfr3; return cpu->isar.id_mmfr3;
case 0xd60: /* ISAR0. */ case 0xd60: /* ISAR0. */
return cpu->isar.id_isar0; return cpu->isar.id_isar0;
case 0xd64: /* ISAR1. */ case 0xd64: /* ISAR1. */

104
target/arm/cpu.c
View file

@ -1960,9 +1960,9 @@ static void arm1136_r2_initfn(Object *obj)
cpu->id_pfr1 = 0x1; cpu->id_pfr1 = 0x1;
cpu->isar.id_dfr0 = 0x2; cpu->isar.id_dfr0 = 0x2;
cpu->id_afr0 = 0x3; cpu->id_afr0 = 0x3;
cpu->id_mmfr0 = 0x01130003; cpu->isar.id_mmfr0 = 0x01130003;
cpu->id_mmfr1 = 0x10030302; cpu->isar.id_mmfr1 = 0x10030302;
cpu->id_mmfr2 = 0x01222110; cpu->isar.id_mmfr2 = 0x01222110;
cpu->isar.id_isar0 = 0x00140011; cpu->isar.id_isar0 = 0x00140011;
cpu->isar.id_isar1 = 0x12002111; cpu->isar.id_isar1 = 0x12002111;
cpu->isar.id_isar2 = 0x11231111; cpu->isar.id_isar2 = 0x11231111;
@ -1992,9 +1992,9 @@ static void arm1136_initfn(Object *obj)
cpu->id_pfr1 = 0x1; cpu->id_pfr1 = 0x1;
cpu->isar.id_dfr0 = 0x2; cpu->isar.id_dfr0 = 0x2;
cpu->id_afr0 = 0x3; cpu->id_afr0 = 0x3;
cpu->id_mmfr0 = 0x01130003; cpu->isar.id_mmfr0 = 0x01130003;
cpu->id_mmfr1 = 0x10030302; cpu->isar.id_mmfr1 = 0x10030302;
cpu->id_mmfr2 = 0x01222110; cpu->isar.id_mmfr2 = 0x01222110;
cpu->isar.id_isar0 = 0x00140011; cpu->isar.id_isar0 = 0x00140011;
cpu->isar.id_isar1 = 0x12002111; cpu->isar.id_isar1 = 0x12002111;
cpu->isar.id_isar2 = 0x11231111; cpu->isar.id_isar2 = 0x11231111;
@ -2025,9 +2025,9 @@ static void arm1176_initfn(Object *obj)
cpu->id_pfr1 = 0x11; cpu->id_pfr1 = 0x11;
cpu->isar.id_dfr0 = 0x33; cpu->isar.id_dfr0 = 0x33;
cpu->id_afr0 = 0; cpu->id_afr0 = 0;
cpu->id_mmfr0 = 0x01130003; cpu->isar.id_mmfr0 = 0x01130003;
cpu->id_mmfr1 = 0x10030302; cpu->isar.id_mmfr1 = 0x10030302;
cpu->id_mmfr2 = 0x01222100; cpu->isar.id_mmfr2 = 0x01222100;
cpu->isar.id_isar0 = 0x0140011; cpu->isar.id_isar0 = 0x0140011;
cpu->isar.id_isar1 = 0x12002111; cpu->isar.id_isar1 = 0x12002111;
cpu->isar.id_isar2 = 0x11231121; cpu->isar.id_isar2 = 0x11231121;
@ -2055,9 +2055,9 @@ static void arm11mpcore_initfn(Object *obj)
cpu->id_pfr1 = 0x1; cpu->id_pfr1 = 0x1;
cpu->isar.id_dfr0 = 0; cpu->isar.id_dfr0 = 0;
cpu->id_afr0 = 0x2; cpu->id_afr0 = 0x2;
cpu->id_mmfr0 = 0x01100103; cpu->isar.id_mmfr0 = 0x01100103;
cpu->id_mmfr1 = 0x10020302; cpu->isar.id_mmfr1 = 0x10020302;
cpu->id_mmfr2 = 0x01222000; cpu->isar.id_mmfr2 = 0x01222000;
cpu->isar.id_isar0 = 0x00100011; cpu->isar.id_isar0 = 0x00100011;
cpu->isar.id_isar1 = 0x12002111; cpu->isar.id_isar1 = 0x12002111;
cpu->isar.id_isar2 = 0x11221011; cpu->isar.id_isar2 = 0x11221011;
@ -2087,10 +2087,10 @@ static void cortex_m3_initfn(Object *obj)
cpu->id_pfr1 = 0x00000200; cpu->id_pfr1 = 0x00000200;
cpu->isar.id_dfr0 = 0x00100000; cpu->isar.id_dfr0 = 0x00100000;
cpu->id_afr0 = 0x00000000; cpu->id_afr0 = 0x00000000;
cpu->id_mmfr0 = 0x00000030; cpu->isar.id_mmfr0 = 0x00000030;
cpu->id_mmfr1 = 0x00000000; cpu->isar.id_mmfr1 = 0x00000000;
cpu->id_mmfr2 = 0x00000000; cpu->isar.id_mmfr2 = 0x00000000;
cpu->id_mmfr3 = 0x00000000; cpu->isar.id_mmfr3 = 0x00000000;
cpu->isar.id_isar0 = 0x01141110; cpu->isar.id_isar0 = 0x01141110;
cpu->isar.id_isar1 = 0x02111000; cpu->isar.id_isar1 = 0x02111000;
cpu->isar.id_isar2 = 0x21112231; cpu->isar.id_isar2 = 0x21112231;
@ -2118,10 +2118,10 @@ static void cortex_m4_initfn(Object *obj)
cpu->id_pfr1 = 0x00000200; cpu->id_pfr1 = 0x00000200;
cpu->isar.id_dfr0 = 0x00100000; cpu->isar.id_dfr0 = 0x00100000;
cpu->id_afr0 = 0x00000000; cpu->id_afr0 = 0x00000000;
cpu->id_mmfr0 = 0x00000030; cpu->isar.id_mmfr0 = 0x00000030;
cpu->id_mmfr1 = 0x00000000; cpu->isar.id_mmfr1 = 0x00000000;
cpu->id_mmfr2 = 0x00000000; cpu->isar.id_mmfr2 = 0x00000000;
cpu->id_mmfr3 = 0x00000000; cpu->isar.id_mmfr3 = 0x00000000;
cpu->isar.id_isar0 = 0x01141110; cpu->isar.id_isar0 = 0x01141110;
cpu->isar.id_isar1 = 0x02111000; cpu->isar.id_isar1 = 0x02111000;
cpu->isar.id_isar2 = 0x21112231; cpu->isar.id_isar2 = 0x21112231;
@ -2149,10 +2149,10 @@ static void cortex_m7_initfn(Object *obj)
cpu->id_pfr1 = 0x00000200; cpu->id_pfr1 = 0x00000200;
cpu->isar.id_dfr0 = 0x00100000; cpu->isar.id_dfr0 = 0x00100000;
cpu->id_afr0 = 0x00000000; cpu->id_afr0 = 0x00000000;
cpu->id_mmfr0 = 0x00100030; cpu->isar.id_mmfr0 = 0x00100030;
cpu->id_mmfr1 = 0x00000000; cpu->isar.id_mmfr1 = 0x00000000;
cpu->id_mmfr2 = 0x01000000; cpu->isar.id_mmfr2 = 0x01000000;
cpu->id_mmfr3 = 0x00000000; cpu->isar.id_mmfr3 = 0x00000000;
cpu->isar.id_isar0 = 0x01101110; cpu->isar.id_isar0 = 0x01101110;
cpu->isar.id_isar1 = 0x02112000; cpu->isar.id_isar1 = 0x02112000;
cpu->isar.id_isar2 = 0x20232231; cpu->isar.id_isar2 = 0x20232231;
@ -2182,10 +2182,10 @@ static void cortex_m33_initfn(Object *obj)
cpu->id_pfr1 = 0x00000210; cpu->id_pfr1 = 0x00000210;
cpu->isar.id_dfr0 = 0x00200000; cpu->isar.id_dfr0 = 0x00200000;
cpu->id_afr0 = 0x00000000; cpu->id_afr0 = 0x00000000;
cpu->id_mmfr0 = 0x00101F40; cpu->isar.id_mmfr0 = 0x00101F40;
cpu->id_mmfr1 = 0x00000000; cpu->isar.id_mmfr1 = 0x00000000;
cpu->id_mmfr2 = 0x01000000; cpu->isar.id_mmfr2 = 0x01000000;
cpu->id_mmfr3 = 0x00000000; cpu->isar.id_mmfr3 = 0x00000000;
cpu->isar.id_isar0 = 0x01101110; cpu->isar.id_isar0 = 0x01101110;
cpu->isar.id_isar1 = 0x02212000; cpu->isar.id_isar1 = 0x02212000;
cpu->isar.id_isar2 = 0x20232232; cpu->isar.id_isar2 = 0x20232232;
@ -2234,10 +2234,10 @@ static void cortex_r5_initfn(Object *obj)
cpu->id_pfr1 = 0x001; cpu->id_pfr1 = 0x001;
cpu->isar.id_dfr0 = 0x010400; cpu->isar.id_dfr0 = 0x010400;
cpu->id_afr0 = 0x0; cpu->id_afr0 = 0x0;
cpu->id_mmfr0 = 0x0210030; cpu->isar.id_mmfr0 = 0x0210030;
cpu->id_mmfr1 = 0x00000000; cpu->isar.id_mmfr1 = 0x00000000;
cpu->id_mmfr2 = 0x01200000; cpu->isar.id_mmfr2 = 0x01200000;
cpu->id_mmfr3 = 0x0211; cpu->isar.id_mmfr3 = 0x0211;
cpu->isar.id_isar0 = 0x02101111; cpu->isar.id_isar0 = 0x02101111;
cpu->isar.id_isar1 = 0x13112111; cpu->isar.id_isar1 = 0x13112111;
cpu->isar.id_isar2 = 0x21232141; cpu->isar.id_isar2 = 0x21232141;
@ -2289,10 +2289,10 @@ static void cortex_a8_initfn(Object *obj)
cpu->id_pfr1 = 0x11; cpu->id_pfr1 = 0x11;
cpu->isar.id_dfr0 = 0x400; cpu->isar.id_dfr0 = 0x400;
cpu->id_afr0 = 0; cpu->id_afr0 = 0;
cpu->id_mmfr0 = 0x31100003; cpu->isar.id_mmfr0 = 0x31100003;
cpu->id_mmfr1 = 0x20000000; cpu->isar.id_mmfr1 = 0x20000000;
cpu->id_mmfr2 = 0x01202000; cpu->isar.id_mmfr2 = 0x01202000;
cpu->id_mmfr3 = 0x11; cpu->isar.id_mmfr3 = 0x11;
cpu->isar.id_isar0 = 0x00101111; cpu->isar.id_isar0 = 0x00101111;
cpu->isar.id_isar1 = 0x12112111; cpu->isar.id_isar1 = 0x12112111;
cpu->isar.id_isar2 = 0x21232031; cpu->isar.id_isar2 = 0x21232031;
@ -2362,10 +2362,10 @@ static void cortex_a9_initfn(Object *obj)
cpu->id_pfr1 = 0x11; cpu->id_pfr1 = 0x11;
cpu->isar.id_dfr0 = 0x000; cpu->isar.id_dfr0 = 0x000;
cpu->id_afr0 = 0; cpu->id_afr0 = 0;
cpu->id_mmfr0 = 0x00100103; cpu->isar.id_mmfr0 = 0x00100103;
cpu->id_mmfr1 = 0x20000000; cpu->isar.id_mmfr1 = 0x20000000;
cpu->id_mmfr2 = 0x01230000; cpu->isar.id_mmfr2 = 0x01230000;
cpu->id_mmfr3 = 0x00002111; cpu->isar.id_mmfr3 = 0x00002111;
cpu->isar.id_isar0 = 0x00101111; cpu->isar.id_isar0 = 0x00101111;
cpu->isar.id_isar1 = 0x13112111; cpu->isar.id_isar1 = 0x13112111;
cpu->isar.id_isar2 = 0x21232041; cpu->isar.id_isar2 = 0x21232041;
@ -2427,10 +2427,10 @@ static void cortex_a7_initfn(Object *obj)
cpu->id_pfr1 = 0x00011011; cpu->id_pfr1 = 0x00011011;
cpu->isar.id_dfr0 = 0x02010555; cpu->isar.id_dfr0 = 0x02010555;
cpu->id_afr0 = 0x00000000; cpu->id_afr0 = 0x00000000;
cpu->id_mmfr0 = 0x10101105; cpu->isar.id_mmfr0 = 0x10101105;
cpu->id_mmfr1 = 0x40000000; cpu->isar.id_mmfr1 = 0x40000000;
cpu->id_mmfr2 = 0x01240000; cpu->isar.id_mmfr2 = 0x01240000;
cpu->id_mmfr3 = 0x02102211; cpu->isar.id_mmfr3 = 0x02102211;
/* a7_mpcore_r0p5_trm, page 4-4 gives 0x01101110; but /* a7_mpcore_r0p5_trm, page 4-4 gives 0x01101110; but
* table 4-41 gives 0x02101110, which includes the arm div insns. * table 4-41 gives 0x02101110, which includes the arm div insns.
*/ */
@ -2473,10 +2473,10 @@ static void cortex_a15_initfn(Object *obj)
cpu->id_pfr1 = 0x00011011; cpu->id_pfr1 = 0x00011011;
cpu->isar.id_dfr0 = 0x02010555; cpu->isar.id_dfr0 = 0x02010555;
cpu->id_afr0 = 0x00000000; cpu->id_afr0 = 0x00000000;
cpu->id_mmfr0 = 0x10201105; cpu->isar.id_mmfr0 = 0x10201105;
cpu->id_mmfr1 = 0x20000000; cpu->isar.id_mmfr1 = 0x20000000;
cpu->id_mmfr2 = 0x01240000; cpu->isar.id_mmfr2 = 0x01240000;
cpu->id_mmfr3 = 0x02102211; cpu->isar.id_mmfr3 = 0x02102211;
cpu->isar.id_isar0 = 0x02101110; cpu->isar.id_isar0 = 0x02101110;
cpu->isar.id_isar1 = 0x13112111; cpu->isar.id_isar1 = 0x13112111;
cpu->isar.id_isar2 = 0x21232041; cpu->isar.id_isar2 = 0x21232041;
@ -2712,13 +2712,13 @@ static void arm_max_initfn(Object *obj)
t = FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */ t = FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */
cpu->isar.mvfr2 = t; cpu->isar.mvfr2 = t;
t = cpu->id_mmfr3; t = cpu->isar.id_mmfr3;
t = FIELD_DP32(t, ID_MMFR3, PAN, 2); /* ATS1E1 */ t = FIELD_DP32(t, ID_MMFR3, PAN, 2); /* ATS1E1 */
cpu->id_mmfr3 = t; cpu->isar.id_mmfr3 = t;
t = cpu->id_mmfr4; t = cpu->isar.id_mmfr4;
t = FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */ t = FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */
cpu->id_mmfr4 = t; cpu->isar.id_mmfr4 = t;
} }
#endif #endif
} }

14
target/arm/cpu.h
View file

@ -867,6 +867,11 @@ struct ARMCPU {
uint32_t id_isar4; uint32_t id_isar4;
uint32_t id_isar5; uint32_t id_isar5;
uint32_t id_isar6; uint32_t id_isar6;
uint32_t id_mmfr0;
uint32_t id_mmfr1;
uint32_t id_mmfr2;
uint32_t id_mmfr3;
uint32_t id_mmfr4;
uint32_t mvfr0; uint32_t mvfr0;
uint32_t mvfr1; uint32_t mvfr1;
uint32_t mvfr2; uint32_t mvfr2;
@ -892,11 +897,6 @@ struct ARMCPU {
uint64_t pmceid0; uint64_t pmceid0;
uint64_t pmceid1; uint64_t pmceid1;
uint32_t id_afr0; uint32_t id_afr0;
uint32_t id_mmfr0;
uint32_t id_mmfr1;
uint32_t id_mmfr2;
uint32_t id_mmfr3;
uint32_t id_mmfr4;
uint64_t id_aa64afr0; uint64_t id_aa64afr0;
uint64_t id_aa64afr1; uint64_t id_aa64afr1;
uint32_t clidr; uint32_t clidr;
@ -3504,12 +3504,12 @@ static inline bool isar_feature_aa32_vminmaxnm(const ARMISARegisters *id)
static inline bool isar_feature_aa32_pan(const ARMISARegisters *id) static inline bool isar_feature_aa32_pan(const ARMISARegisters *id)
{ {
return FIELD_EX64(id->mvfr0, ID_MMFR3, PAN) != 0; return FIELD_EX32(id->id_mmfr3, ID_MMFR3, PAN) != 0;
} }
static inline bool isar_feature_aa32_ats1e1(const ARMISARegisters *id) static inline bool isar_feature_aa32_ats1e1(const ARMISARegisters *id)
{ {
return FIELD_EX64(id->mvfr0, ID_MMFR3, PAN) >= 2; return FIELD_EX32(id->id_mmfr3, ID_MMFR3, PAN) >= 2;
} }
static inline bool isar_feature_aa32_pmu_8_1(const ARMISARegisters *id) static inline bool isar_feature_aa32_pmu_8_1(const ARMISARegisters *id)

28
target/arm/cpu64.c
View file

@ -123,10 +123,10 @@ static void aarch64_a57_initfn(Object *obj)
cpu->id_pfr1 = 0x00011011; cpu->id_pfr1 = 0x00011011;
cpu->isar.id_dfr0 = 0x03010066; cpu->isar.id_dfr0 = 0x03010066;
cpu->id_afr0 = 0x00000000; cpu->id_afr0 = 0x00000000;
cpu->id_mmfr0 = 0x10101105; cpu->isar.id_mmfr0 = 0x10101105;
cpu->id_mmfr1 = 0x40000000; cpu->isar.id_mmfr1 = 0x40000000;
cpu->id_mmfr2 = 0x01260000; cpu->isar.id_mmfr2 = 0x01260000;
cpu->id_mmfr3 = 0x02102211; cpu->isar.id_mmfr3 = 0x02102211;
cpu->isar.id_isar0 = 0x02101110; cpu->isar.id_isar0 = 0x02101110;
cpu->isar.id_isar1 = 0x13112111; cpu->isar.id_isar1 = 0x13112111;
cpu->isar.id_isar2 = 0x21232042; cpu->isar.id_isar2 = 0x21232042;
@ -177,10 +177,10 @@ static void aarch64_a53_initfn(Object *obj)
cpu->id_pfr1 = 0x00011011; cpu->id_pfr1 = 0x00011011;
cpu->isar.id_dfr0 = 0x03010066; cpu->isar.id_dfr0 = 0x03010066;
cpu->id_afr0 = 0x00000000; cpu->id_afr0 = 0x00000000;
cpu->id_mmfr0 = 0x10101105; cpu->isar.id_mmfr0 = 0x10101105;
cpu->id_mmfr1 = 0x40000000; cpu->isar.id_mmfr1 = 0x40000000;
cpu->id_mmfr2 = 0x01260000; cpu->isar.id_mmfr2 = 0x01260000;
cpu->id_mmfr3 = 0x02102211; cpu->isar.id_mmfr3 = 0x02102211;
cpu->isar.id_isar0 = 0x02101110; cpu->isar.id_isar0 = 0x02101110;
cpu->isar.id_isar1 = 0x13112111; cpu->isar.id_isar1 = 0x13112111;
cpu->isar.id_isar2 = 0x21232042; cpu->isar.id_isar2 = 0x21232042;
@ -230,10 +230,10 @@ static void aarch64_a72_initfn(Object *obj)
cpu->id_pfr1 = 0x00011011; cpu->id_pfr1 = 0x00011011;
cpu->isar.id_dfr0 = 0x03010066; cpu->isar.id_dfr0 = 0x03010066;
cpu->id_afr0 = 0x00000000; cpu->id_afr0 = 0x00000000;
cpu->id_mmfr0 = 0x10201105; cpu->isar.id_mmfr0 = 0x10201105;
cpu->id_mmfr1 = 0x40000000; cpu->isar.id_mmfr1 = 0x40000000;
cpu->id_mmfr2 = 0x01260000; cpu->isar.id_mmfr2 = 0x01260000;
cpu->id_mmfr3 = 0x02102211; cpu->isar.id_mmfr3 = 0x02102211;
cpu->isar.id_isar0 = 0x02101110; cpu->isar.id_isar0 = 0x02101110;
cpu->isar.id_isar1 = 0x13112111; cpu->isar.id_isar1 = 0x13112111;
cpu->isar.id_isar2 = 0x21232042; cpu->isar.id_isar2 = 0x21232042;
@ -699,9 +699,9 @@ static void aarch64_max_initfn(Object *obj)
u = FIELD_DP32(u, ID_ISAR6, SPECRES, 1); u = FIELD_DP32(u, ID_ISAR6, SPECRES, 1);
cpu->isar.id_isar6 = u; cpu->isar.id_isar6 = u;
u = cpu->id_mmfr3; u = cpu->isar.id_mmfr3;
u = FIELD_DP32(u, ID_MMFR3, PAN, 2); /* ATS1E1 */ u = FIELD_DP32(u, ID_MMFR3, PAN, 2); /* ATS1E1 */
cpu->id_mmfr3 = u; cpu->isar.id_mmfr3 = u;
u = cpu->isar.id_aa64dfr0; u = cpu->isar.id_aa64dfr0;
u = FIELD_DP64(u, ID_AA64DFR0, PMUVER, 5); /* v8.4-PMU */ u = FIELD_DP64(u, ID_AA64DFR0, PMUVER, 5); /* v8.4-PMU */

12
target/arm/helper.c
View file

@ -6910,22 +6910,22 @@ void register_cp_regs_for_features(ARMCPU *cpu)
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 4, .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 4,
.access = PL1_R, .type = ARM_CP_CONST, .access = PL1_R, .type = ARM_CP_CONST,
.accessfn = access_aa32_tid3, .accessfn = access_aa32_tid3,
.resetvalue = cpu->id_mmfr0 }, .resetvalue = cpu->isar.id_mmfr0 },
{ .name = "ID_MMFR1", .state = ARM_CP_STATE_BOTH, { .name = "ID_MMFR1", .state = ARM_CP_STATE_BOTH,
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 5, .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 5,
.access = PL1_R, .type = ARM_CP_CONST, .access = PL1_R, .type = ARM_CP_CONST,
.accessfn = access_aa32_tid3, .accessfn = access_aa32_tid3,
.resetvalue = cpu->id_mmfr1 }, .resetvalue = cpu->isar.id_mmfr1 },
{ .name = "ID_MMFR2", .state = ARM_CP_STATE_BOTH, { .name = "ID_MMFR2", .state = ARM_CP_STATE_BOTH,
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 6, .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 6,
.access = PL1_R, .type = ARM_CP_CONST, .access = PL1_R, .type = ARM_CP_CONST,
.accessfn = access_aa32_tid3, .accessfn = access_aa32_tid3,
.resetvalue = cpu->id_mmfr2 }, .resetvalue = cpu->isar.id_mmfr2 },
{ .name = "ID_MMFR3", .state = ARM_CP_STATE_BOTH, { .name = "ID_MMFR3", .state = ARM_CP_STATE_BOTH,
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 7, .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 7,
.access = PL1_R, .type = ARM_CP_CONST, .access = PL1_R, .type = ARM_CP_CONST,
.accessfn = access_aa32_tid3, .accessfn = access_aa32_tid3,
.resetvalue = cpu->id_mmfr3 }, .resetvalue = cpu->isar.id_mmfr3 },
{ .name = "ID_ISAR0", .state = ARM_CP_STATE_BOTH, { .name = "ID_ISAR0", .state = ARM_CP_STATE_BOTH,
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 0, .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 0,
.access = PL1_R, .type = ARM_CP_CONST, .access = PL1_R, .type = ARM_CP_CONST,
@ -6960,7 +6960,7 @@ void register_cp_regs_for_features(ARMCPU *cpu)
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 6, .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 6,
.access = PL1_R, .type = ARM_CP_CONST, .access = PL1_R, .type = ARM_CP_CONST,
.accessfn = access_aa32_tid3, .accessfn = access_aa32_tid3,
.resetvalue = cpu->id_mmfr4 }, .resetvalue = cpu->isar.id_mmfr4 },
{ .name = "ID_ISAR6", .state = ARM_CP_STATE_BOTH, { .name = "ID_ISAR6", .state = ARM_CP_STATE_BOTH,
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 7, .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 7,
.access = PL1_R, .type = ARM_CP_CONST, .access = PL1_R, .type = ARM_CP_CONST,
@ -7409,7 +7409,7 @@ void register_cp_regs_for_features(ARMCPU *cpu)
define_arm_cp_regs(cpu, vmsa_pmsa_cp_reginfo); define_arm_cp_regs(cpu, vmsa_pmsa_cp_reginfo);
define_arm_cp_regs(cpu, vmsa_cp_reginfo); define_arm_cp_regs(cpu, vmsa_cp_reginfo);
/* TTCBR2 is introduced with ARMv8.2-A32HPD. */ /* TTCBR2 is introduced with ARMv8.2-A32HPD. */
if (FIELD_EX32(cpu->id_mmfr4, ID_MMFR4, HPDS) != 0) { if (FIELD_EX32(cpu->isar.id_mmfr4, ID_MMFR4, HPDS) != 0) {
define_one_arm_cp_reg(cpu, &ttbcr2_reginfo); define_one_arm_cp_reg(cpu, &ttbcr2_reginfo);
} }
} }

17
target/arm/kvm32.c
View file

@ -111,6 +111,23 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
* Fortunately there is not yet anything in there that affects migration. * Fortunately there is not yet anything in there that affects migration.
*/ */
err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr0,
ARM_CP15_REG32(0, 0, 1, 4));
err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr1,
ARM_CP15_REG32(0, 0, 1, 5));
err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr2,
ARM_CP15_REG32(0, 0, 1, 6));
err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr3,
ARM_CP15_REG32(0, 0, 1, 7));
if (read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr4,
ARM_CP15_REG32(0, 0, 2, 6))) {
/*
* Older kernels don't support reading ID_MMFR4 (a new in v8
* register); assume it's zero.
*/
ahcf->isar.id_mmfr4 = 0;
}
/* /*
* There is no way to read DBGDIDR, because currently 32-bit KVM * There is no way to read DBGDIDR, because currently 32-bit KVM
* doesn't implement debug at all. Leave it at zero. * doesn't implement debug at all. Leave it at zero.

10
target/arm/kvm64.c
View file

@ -565,6 +565,14 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
*/ */
err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_dfr0, err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_dfr0,
ARM64_SYS_REG(3, 0, 0, 1, 2)); ARM64_SYS_REG(3, 0, 0, 1, 2));
err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr0,
ARM64_SYS_REG(3, 0, 0, 1, 4));
err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr1,
ARM64_SYS_REG(3, 0, 0, 1, 5));
err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr2,
ARM64_SYS_REG(3, 0, 0, 1, 6));
err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr3,
ARM64_SYS_REG(3, 0, 0, 1, 7));
err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar0, err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar0,
ARM64_SYS_REG(3, 0, 0, 2, 0)); ARM64_SYS_REG(3, 0, 0, 2, 0));
err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar1, err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar1,
@ -577,6 +585,8 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
ARM64_SYS_REG(3, 0, 0, 2, 4)); ARM64_SYS_REG(3, 0, 0, 2, 4));
err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar5, err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar5,
ARM64_SYS_REG(3, 0, 0, 2, 5)); ARM64_SYS_REG(3, 0, 0, 2, 5));
err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr4,
ARM64_SYS_REG(3, 0, 0, 2, 6));
err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar6, err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar6,
ARM64_SYS_REG(3, 0, 0, 2, 7)); ARM64_SYS_REG(3, 0, 0, 2, 7));