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target/arm: Test correct register in aa32_pan and aa32_ats1e1 checks

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The isar_feature_aa32_pan and isar_feature_aa32_ats1e1 functions
are supposed to be testing fields in ID_MMFR3; but a cut-and-paste
error meant we were looking at MVFR0 instead.

Fix the functions to look at the right register; this requires
us to move at least id_mmfr3 to the ARMISARegisters struct; we
choose to move all the ID_MMFRn registers for consistency.

Fixes: 3d6ad6bb46
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200214175116.9164-19-peter.maydell@linaro.org
This commit is contained in:
Peter Maydell 2020-02-14 17:51:13 +00:00
parent 62d96ff485
commit 10054016ed
7 changed files with 110 additions and 83 deletions
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14
target/arm/cpu.h
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@ -867,6 +867,11 @@ struct ARMCPU {
uint32_t id_isar4;
uint32_t id_isar5;
uint32_t id_isar6;
uint32_t id_mmfr0;
uint32_t id_mmfr1;
uint32_t id_mmfr2;
uint32_t id_mmfr3;
uint32_t id_mmfr4;
uint32_t mvfr0;
uint32_t mvfr1;
uint32_t mvfr2;
@ -892,11 +897,6 @@ struct ARMCPU {
uint64_t pmceid0;
uint64_t pmceid1;
uint32_t id_afr0;
uint32_t id_mmfr0;
uint32_t id_mmfr1;
uint32_t id_mmfr2;
uint32_t id_mmfr3;
uint32_t id_mmfr4;
uint64_t id_aa64afr0;
uint64_t id_aa64afr1;
uint32_t clidr;
@ -3504,12 +3504,12 @@ static inline bool isar_feature_aa32_vminmaxnm(const ARMISARegisters *id)
static inline bool isar_feature_aa32_pan(const ARMISARegisters *id)
{
return FIELD_EX64(id->mvfr0, ID_MMFR3, PAN) != 0;
return FIELD_EX32(id->id_mmfr3, ID_MMFR3, PAN) != 0;
}
static inline bool isar_feature_aa32_ats1e1(const ARMISARegisters *id)
{
return FIELD_EX64(id->mvfr0, ID_MMFR3, PAN) >= 2;
return FIELD_EX32(id->id_mmfr3, ID_MMFR3, PAN) >= 2;
}
static inline bool isar_feature_aa32_pmu_8_1(const ARMISARegisters *id)