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target/arm: Test correct register in aa32_pan and aa32_ats1e1 checks
The isar_feature_aa32_pan and isar_feature_aa32_ats1e1 functions
are supposed to be testing fields in ID_MMFR3; but a cut-and-paste
error meant we were looking at MVFR0 instead.
Fix the functions to look at the right register; this requires
us to move at least id_mmfr3 to the ARMISARegisters struct; we
choose to move all the ID_MMFRn registers for consistency.
Fixes: 3d6ad6bb46
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200214175116.9164-19-peter.maydell@linaro.org
This commit is contained in:
Peter Maydell
parent
62d96ff485
commit
10054016ed
7 changed files with 110 additions and 83 deletions
104
target/arm/cpu.c
104
target/arm/cpu.c
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@ -1960,9 +1960,9 @@ static void arm1136_r2_initfn(Object *obj)
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cpu->id_pfr1 = 0x1;
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cpu->isar.id_dfr0 = 0x2;
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cpu->id_afr0 = 0x3;
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cpu->id_mmfr0 = 0x01130003;
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cpu->id_mmfr1 = 0x10030302;
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cpu->id_mmfr2 = 0x01222110;
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cpu->isar.id_mmfr0 = 0x01130003;
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cpu->isar.id_mmfr1 = 0x10030302;
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cpu->isar.id_mmfr2 = 0x01222110;
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cpu->isar.id_isar0 = 0x00140011;
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cpu->isar.id_isar1 = 0x12002111;
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cpu->isar.id_isar2 = 0x11231111;
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@ -1992,9 +1992,9 @@ static void arm1136_initfn(Object *obj)
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cpu->id_pfr1 = 0x1;
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cpu->isar.id_dfr0 = 0x2;
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cpu->id_afr0 = 0x3;
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cpu->id_mmfr0 = 0x01130003;
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cpu->id_mmfr1 = 0x10030302;
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cpu->id_mmfr2 = 0x01222110;
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cpu->isar.id_mmfr0 = 0x01130003;
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cpu->isar.id_mmfr1 = 0x10030302;
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cpu->isar.id_mmfr2 = 0x01222110;
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cpu->isar.id_isar0 = 0x00140011;
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cpu->isar.id_isar1 = 0x12002111;
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cpu->isar.id_isar2 = 0x11231111;
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@ -2025,9 +2025,9 @@ static void arm1176_initfn(Object *obj)
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cpu->id_pfr1 = 0x11;
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cpu->isar.id_dfr0 = 0x33;
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cpu->id_afr0 = 0;
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cpu->id_mmfr0 = 0x01130003;
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cpu->id_mmfr1 = 0x10030302;
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cpu->id_mmfr2 = 0x01222100;
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cpu->isar.id_mmfr0 = 0x01130003;
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cpu->isar.id_mmfr1 = 0x10030302;
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cpu->isar.id_mmfr2 = 0x01222100;
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cpu->isar.id_isar0 = 0x0140011;
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cpu->isar.id_isar1 = 0x12002111;
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cpu->isar.id_isar2 = 0x11231121;
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@ -2055,9 +2055,9 @@ static void arm11mpcore_initfn(Object *obj)
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cpu->id_pfr1 = 0x1;
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cpu->isar.id_dfr0 = 0;
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cpu->id_afr0 = 0x2;
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cpu->id_mmfr0 = 0x01100103;
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cpu->id_mmfr1 = 0x10020302;
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cpu->id_mmfr2 = 0x01222000;
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cpu->isar.id_mmfr0 = 0x01100103;
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cpu->isar.id_mmfr1 = 0x10020302;
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cpu->isar.id_mmfr2 = 0x01222000;
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cpu->isar.id_isar0 = 0x00100011;
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cpu->isar.id_isar1 = 0x12002111;
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cpu->isar.id_isar2 = 0x11221011;
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@ -2087,10 +2087,10 @@ static void cortex_m3_initfn(Object *obj)
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cpu->id_pfr1 = 0x00000200;
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cpu->isar.id_dfr0 = 0x00100000;
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cpu->id_afr0 = 0x00000000;
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cpu->id_mmfr0 = 0x00000030;
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cpu->id_mmfr1 = 0x00000000;
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cpu->id_mmfr2 = 0x00000000;
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cpu->id_mmfr3 = 0x00000000;
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cpu->isar.id_mmfr0 = 0x00000030;
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cpu->isar.id_mmfr1 = 0x00000000;
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cpu->isar.id_mmfr2 = 0x00000000;
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cpu->isar.id_mmfr3 = 0x00000000;
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cpu->isar.id_isar0 = 0x01141110;
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cpu->isar.id_isar1 = 0x02111000;
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cpu->isar.id_isar2 = 0x21112231;
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@ -2118,10 +2118,10 @@ static void cortex_m4_initfn(Object *obj)
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cpu->id_pfr1 = 0x00000200;
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cpu->isar.id_dfr0 = 0x00100000;
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cpu->id_afr0 = 0x00000000;
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cpu->id_mmfr0 = 0x00000030;
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cpu->id_mmfr1 = 0x00000000;
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cpu->id_mmfr2 = 0x00000000;
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cpu->id_mmfr3 = 0x00000000;
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cpu->isar.id_mmfr0 = 0x00000030;
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cpu->isar.id_mmfr1 = 0x00000000;
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cpu->isar.id_mmfr2 = 0x00000000;
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cpu->isar.id_mmfr3 = 0x00000000;
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cpu->isar.id_isar0 = 0x01141110;
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cpu->isar.id_isar1 = 0x02111000;
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cpu->isar.id_isar2 = 0x21112231;
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@ -2149,10 +2149,10 @@ static void cortex_m7_initfn(Object *obj)
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cpu->id_pfr1 = 0x00000200;
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cpu->isar.id_dfr0 = 0x00100000;
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cpu->id_afr0 = 0x00000000;
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cpu->id_mmfr0 = 0x00100030;
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cpu->id_mmfr1 = 0x00000000;
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cpu->id_mmfr2 = 0x01000000;
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cpu->id_mmfr3 = 0x00000000;
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cpu->isar.id_mmfr0 = 0x00100030;
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cpu->isar.id_mmfr1 = 0x00000000;
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cpu->isar.id_mmfr2 = 0x01000000;
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cpu->isar.id_mmfr3 = 0x00000000;
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cpu->isar.id_isar0 = 0x01101110;
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cpu->isar.id_isar1 = 0x02112000;
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cpu->isar.id_isar2 = 0x20232231;
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@ -2182,10 +2182,10 @@ static void cortex_m33_initfn(Object *obj)
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cpu->id_pfr1 = 0x00000210;
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cpu->isar.id_dfr0 = 0x00200000;
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cpu->id_afr0 = 0x00000000;
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cpu->id_mmfr0 = 0x00101F40;
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cpu->id_mmfr1 = 0x00000000;
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cpu->id_mmfr2 = 0x01000000;
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cpu->id_mmfr3 = 0x00000000;
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cpu->isar.id_mmfr0 = 0x00101F40;
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cpu->isar.id_mmfr1 = 0x00000000;
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cpu->isar.id_mmfr2 = 0x01000000;
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cpu->isar.id_mmfr3 = 0x00000000;
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cpu->isar.id_isar0 = 0x01101110;
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cpu->isar.id_isar1 = 0x02212000;
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cpu->isar.id_isar2 = 0x20232232;
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@ -2234,10 +2234,10 @@ static void cortex_r5_initfn(Object *obj)
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cpu->id_pfr1 = 0x001;
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cpu->isar.id_dfr0 = 0x010400;
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cpu->id_afr0 = 0x0;
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cpu->id_mmfr0 = 0x0210030;
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cpu->id_mmfr1 = 0x00000000;
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cpu->id_mmfr2 = 0x01200000;
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cpu->id_mmfr3 = 0x0211;
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cpu->isar.id_mmfr0 = 0x0210030;
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cpu->isar.id_mmfr1 = 0x00000000;
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cpu->isar.id_mmfr2 = 0x01200000;
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cpu->isar.id_mmfr3 = 0x0211;
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cpu->isar.id_isar0 = 0x02101111;
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cpu->isar.id_isar1 = 0x13112111;
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cpu->isar.id_isar2 = 0x21232141;
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@ -2289,10 +2289,10 @@ static void cortex_a8_initfn(Object *obj)
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cpu->id_pfr1 = 0x11;
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cpu->isar.id_dfr0 = 0x400;
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cpu->id_afr0 = 0;
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cpu->id_mmfr0 = 0x31100003;
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cpu->id_mmfr1 = 0x20000000;
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cpu->id_mmfr2 = 0x01202000;
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cpu->id_mmfr3 = 0x11;
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cpu->isar.id_mmfr0 = 0x31100003;
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cpu->isar.id_mmfr1 = 0x20000000;
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cpu->isar.id_mmfr2 = 0x01202000;
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cpu->isar.id_mmfr3 = 0x11;
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cpu->isar.id_isar0 = 0x00101111;
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cpu->isar.id_isar1 = 0x12112111;
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cpu->isar.id_isar2 = 0x21232031;
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@ -2362,10 +2362,10 @@ static void cortex_a9_initfn(Object *obj)
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cpu->id_pfr1 = 0x11;
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cpu->isar.id_dfr0 = 0x000;
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cpu->id_afr0 = 0;
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cpu->id_mmfr0 = 0x00100103;
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cpu->id_mmfr1 = 0x20000000;
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cpu->id_mmfr2 = 0x01230000;
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cpu->id_mmfr3 = 0x00002111;
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cpu->isar.id_mmfr0 = 0x00100103;
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cpu->isar.id_mmfr1 = 0x20000000;
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cpu->isar.id_mmfr2 = 0x01230000;
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cpu->isar.id_mmfr3 = 0x00002111;
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cpu->isar.id_isar0 = 0x00101111;
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cpu->isar.id_isar1 = 0x13112111;
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cpu->isar.id_isar2 = 0x21232041;
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@ -2427,10 +2427,10 @@ static void cortex_a7_initfn(Object *obj)
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cpu->id_pfr1 = 0x00011011;
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cpu->isar.id_dfr0 = 0x02010555;
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cpu->id_afr0 = 0x00000000;
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cpu->id_mmfr0 = 0x10101105;
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cpu->id_mmfr1 = 0x40000000;
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cpu->id_mmfr2 = 0x01240000;
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cpu->id_mmfr3 = 0x02102211;
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cpu->isar.id_mmfr0 = 0x10101105;
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cpu->isar.id_mmfr1 = 0x40000000;
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cpu->isar.id_mmfr2 = 0x01240000;
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cpu->isar.id_mmfr3 = 0x02102211;
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/* a7_mpcore_r0p5_trm, page 4-4 gives 0x01101110; but
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* table 4-41 gives 0x02101110, which includes the arm div insns.
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*/
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@ -2473,10 +2473,10 @@ static void cortex_a15_initfn(Object *obj)
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cpu->id_pfr1 = 0x00011011;
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cpu->isar.id_dfr0 = 0x02010555;
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cpu->id_afr0 = 0x00000000;
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cpu->id_mmfr0 = 0x10201105;
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cpu->id_mmfr1 = 0x20000000;
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cpu->id_mmfr2 = 0x01240000;
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cpu->id_mmfr3 = 0x02102211;
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cpu->isar.id_mmfr0 = 0x10201105;
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cpu->isar.id_mmfr1 = 0x20000000;
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cpu->isar.id_mmfr2 = 0x01240000;
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cpu->isar.id_mmfr3 = 0x02102211;
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cpu->isar.id_isar0 = 0x02101110;
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cpu->isar.id_isar1 = 0x13112111;
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cpu->isar.id_isar2 = 0x21232041;
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@ -2712,13 +2712,13 @@ static void arm_max_initfn(Object *obj)
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t = FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */
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cpu->isar.mvfr2 = t;
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t = cpu->id_mmfr3;
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t = cpu->isar.id_mmfr3;
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t = FIELD_DP32(t, ID_MMFR3, PAN, 2); /* ATS1E1 */
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cpu->id_mmfr3 = t;
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cpu->isar.id_mmfr3 = t;
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t = cpu->id_mmfr4;
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t = cpu->isar.id_mmfr4;
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t = FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */
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cpu->id_mmfr4 = t;
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cpu->isar.id_mmfr4 = t;
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}
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#endif
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}
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