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target/arm: Test correct register in aa32_pan and aa32_ats1e1 checks

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The isar_feature_aa32_pan and isar_feature_aa32_ats1e1 functions
are supposed to be testing fields in ID_MMFR3; but a cut-and-paste
error meant we were looking at MVFR0 instead.

Fix the functions to look at the right register; this requires
us to move at least id_mmfr3 to the ARMISARegisters struct; we
choose to move all the ID_MMFRn registers for consistency.

Fixes: 3d6ad6bb46
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200214175116.9164-19-peter.maydell@linaro.org
This commit is contained in:
Peter Maydell 2020-02-14 17:51:13 +00:00
parent 62d96ff485
commit 10054016ed
7 changed files with 110 additions and 83 deletions
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8
hw/intc/armv7m_nvic.c
View file

@ -1231,13 +1231,13 @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs)
case 0xd4c: /* AFR0. */
return cpu->id_afr0;
case 0xd50: /* MMFR0. */
return cpu->id_mmfr0;
return cpu->isar.id_mmfr0;
case 0xd54: /* MMFR1. */
return cpu->id_mmfr1;
return cpu->isar.id_mmfr1;
case 0xd58: /* MMFR2. */
return cpu->id_mmfr2;
return cpu->isar.id_mmfr2;
case 0xd5c: /* MMFR3. */
return cpu->id_mmfr3;
return cpu->isar.id_mmfr3;
case 0xd60: /* ISAR0. */
return cpu->isar.id_isar0;
case 0xd64: /* ISAR1. */