mirror of
https://github.com/Motorhead1991/qemu.git
synced 2025-08-03 15:53:54 -06:00
target/ppc: Move TCG specific exception handlers to tcg-excp_helper.c
Move the TCGCPUOps handlers to a new unit: tcg-excp_helper.c,
only built when TCG is selected.
See in target/ppc/cpu_init.c:
#ifdef CONFIG_TCG
static const TCGCPUOps ppc_tcg_ops = {
...
.do_unaligned_access = ppc_cpu_do_unaligned_access,
.do_transaction_failed = ppc_cpu_do_transaction_failed,
.debug_excp_handler = ppc_cpu_debug_excp_handler,
.debug_check_breakpoint = ppc_cpu_debug_check_breakpoint,
.debug_check_watchpoint = ppc_cpu_debug_check_watchpoint,
};
#endif /* CONFIG_TCG */
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Harsh Prateek Bora <harshpb@linux.ibm.com>
Message-ID: <20250127102620.39159-5-philmd@linaro.org>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
This commit is contained in:
Philippe Mathieu-Daudé
Nicholas Piggin
parent
215b2ee8f1
commit
0fc76338fe
3 changed files with 203 additions and 173 deletions
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@ -3144,178 +3144,5 @@ void helper_book3s_trace(CPUPPCState *env, target_ulong prev_ip)
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raise_exception_err(env, POWERPC_EXCP_TRACE, error_code);
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}
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void ppc_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr,
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MMUAccessType access_type,
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int mmu_idx, uintptr_t retaddr)
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{
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CPUPPCState *env = cpu_env(cs);
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uint32_t insn;
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/* Restore state and reload the insn we executed, for filling in DSISR. */
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cpu_restore_state(cs, retaddr);
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insn = ppc_ldl_code(env, env->nip);
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switch (env->mmu_model) {
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case POWERPC_MMU_SOFT_4xx:
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env->spr[SPR_40x_DEAR] = vaddr;
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break;
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case POWERPC_MMU_BOOKE:
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case POWERPC_MMU_BOOKE206:
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env->spr[SPR_BOOKE_DEAR] = vaddr;
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break;
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default:
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env->spr[SPR_DAR] = vaddr;
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break;
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}
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cs->exception_index = POWERPC_EXCP_ALIGN;
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env->error_code = insn & 0x03FF0000;
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cpu_loop_exit(cs);
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}
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void ppc_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
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vaddr vaddr, unsigned size,
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MMUAccessType access_type,
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int mmu_idx, MemTxAttrs attrs,
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MemTxResult response, uintptr_t retaddr)
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{
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CPUPPCState *env = cpu_env(cs);
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switch (env->excp_model) {
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#if defined(TARGET_PPC64)
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case POWERPC_EXCP_POWER8:
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case POWERPC_EXCP_POWER9:
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case POWERPC_EXCP_POWER10:
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case POWERPC_EXCP_POWER11:
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/*
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* Machine check codes can be found in processor User Manual or
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* Linux or skiboot source.
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*/
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if (access_type == MMU_DATA_LOAD) {
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env->spr[SPR_DAR] = vaddr;
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env->spr[SPR_DSISR] = PPC_BIT(57);
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env->error_code = PPC_BIT(42);
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} else if (access_type == MMU_DATA_STORE) {
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/*
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* MCE for stores in POWER is asynchronous so hardware does
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* not set DAR, but QEMU can do better.
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*/
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env->spr[SPR_DAR] = vaddr;
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env->error_code = PPC_BIT(36) | PPC_BIT(43) | PPC_BIT(45);
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env->error_code |= PPC_BIT(42);
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} else { /* Fetch */
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/*
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* is_prefix_insn_excp() tests !PPC_BIT(42) to avoid fetching
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* the instruction, so that must always be clear for fetches.
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*/
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env->error_code = PPC_BIT(36) | PPC_BIT(44) | PPC_BIT(45);
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}
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break;
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#endif
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default:
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/*
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* TODO: Check behaviour for other CPUs, for now do nothing.
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* Could add a basic MCE even if real hardware ignores.
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*/
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return;
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}
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cs->exception_index = POWERPC_EXCP_MCHECK;
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cpu_loop_exit_restore(cs, retaddr);
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}
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void ppc_cpu_debug_excp_handler(CPUState *cs)
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{
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#if defined(TARGET_PPC64)
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CPUPPCState *env = cpu_env(cs);
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if (env->insns_flags2 & PPC2_ISA207S) {
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if (cs->watchpoint_hit) {
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if (cs->watchpoint_hit->flags & BP_CPU) {
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env->spr[SPR_DAR] = cs->watchpoint_hit->hitaddr;
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env->spr[SPR_DSISR] = PPC_BIT(41);
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cs->watchpoint_hit = NULL;
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raise_exception(env, POWERPC_EXCP_DSI);
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}
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cs->watchpoint_hit = NULL;
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} else if (cpu_breakpoint_test(cs, env->nip, BP_CPU)) {
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raise_exception_err(env, POWERPC_EXCP_TRACE,
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PPC_BIT(33) | PPC_BIT(43));
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}
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}
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#endif
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}
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bool ppc_cpu_debug_check_breakpoint(CPUState *cs)
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{
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#if defined(TARGET_PPC64)
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CPUPPCState *env = cpu_env(cs);
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if (env->insns_flags2 & PPC2_ISA207S) {
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target_ulong priv;
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priv = env->spr[SPR_CIABR] & PPC_BITMASK(62, 63);
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switch (priv) {
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case 0x1: /* problem */
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return env->msr & ((target_ulong)1 << MSR_PR);
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case 0x2: /* supervisor */
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return (!(env->msr & ((target_ulong)1 << MSR_PR)) &&
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!(env->msr & ((target_ulong)1 << MSR_HV)));
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case 0x3: /* hypervisor */
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return (!(env->msr & ((target_ulong)1 << MSR_PR)) &&
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(env->msr & ((target_ulong)1 << MSR_HV)));
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default:
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g_assert_not_reached();
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}
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}
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#endif
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return false;
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}
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bool ppc_cpu_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp)
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{
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#if defined(TARGET_PPC64)
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CPUPPCState *env = cpu_env(cs);
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if (env->insns_flags2 & PPC2_ISA207S) {
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if (wp == env->dawr0_watchpoint) {
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uint32_t dawrx = env->spr[SPR_DAWRX0];
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bool wt = extract32(dawrx, PPC_BIT_NR(59), 1);
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bool wti = extract32(dawrx, PPC_BIT_NR(60), 1);
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bool hv = extract32(dawrx, PPC_BIT_NR(61), 1);
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bool sv = extract32(dawrx, PPC_BIT_NR(62), 1);
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bool pr = extract32(dawrx, PPC_BIT_NR(62), 1);
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if ((env->msr & ((target_ulong)1 << MSR_PR)) && !pr) {
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return false;
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} else if ((env->msr & ((target_ulong)1 << MSR_HV)) && !hv) {
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return false;
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} else if (!sv) {
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return false;
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}
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if (!wti) {
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if (env->msr & ((target_ulong)1 << MSR_DR)) {
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if (!wt) {
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return false;
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}
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} else {
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if (wt) {
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return false;
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}
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}
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}
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return true;
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}
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}
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#endif
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return false;
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}
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#endif /* !CONFIG_USER_ONLY */
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#endif /* CONFIG_TCG */
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@ -14,6 +14,7 @@ ppc_ss.add(when: 'CONFIG_TCG', if_true: files(
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'int_helper.c',
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'mem_helper.c',
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'misc_helper.c',
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'tcg-excp_helper.c',
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'timebase_helper.c',
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'translate.c',
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'power8-pmu.c',
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202
target/ppc/tcg-excp_helper.c
Normal file
202
target/ppc/tcg-excp_helper.c
Normal file
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@ -0,0 +1,202 @@
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/*
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* PowerPC exception emulation helpers for QEMU (TCG specific)
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*
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* Copyright (c) 2003-2007 Jocelyn Mayer
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "exec/cpu_ldst.h"
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#include "hw/ppc/ppc.h"
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#include "internal.h"
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#include "cpu.h"
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#include "trace.h"
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#ifndef CONFIG_USER_ONLY
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void ppc_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr,
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MMUAccessType access_type,
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int mmu_idx, uintptr_t retaddr)
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{
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CPUPPCState *env = cpu_env(cs);
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uint32_t insn;
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/* Restore state and reload the insn we executed, for filling in DSISR. */
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cpu_restore_state(cs, retaddr);
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insn = ppc_ldl_code(env, env->nip);
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switch (env->mmu_model) {
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case POWERPC_MMU_SOFT_4xx:
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env->spr[SPR_40x_DEAR] = vaddr;
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break;
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case POWERPC_MMU_BOOKE:
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case POWERPC_MMU_BOOKE206:
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env->spr[SPR_BOOKE_DEAR] = vaddr;
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break;
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default:
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env->spr[SPR_DAR] = vaddr;
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break;
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}
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cs->exception_index = POWERPC_EXCP_ALIGN;
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env->error_code = insn & 0x03FF0000;
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cpu_loop_exit(cs);
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}
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void ppc_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
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vaddr vaddr, unsigned size,
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MMUAccessType access_type,
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int mmu_idx, MemTxAttrs attrs,
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MemTxResult response, uintptr_t retaddr)
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{
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CPUPPCState *env = cpu_env(cs);
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switch (env->excp_model) {
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#if defined(TARGET_PPC64)
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case POWERPC_EXCP_POWER8:
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case POWERPC_EXCP_POWER9:
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case POWERPC_EXCP_POWER10:
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case POWERPC_EXCP_POWER11:
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/*
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* Machine check codes can be found in processor User Manual or
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* Linux or skiboot source.
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*/
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if (access_type == MMU_DATA_LOAD) {
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env->spr[SPR_DAR] = vaddr;
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env->spr[SPR_DSISR] = PPC_BIT(57);
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env->error_code = PPC_BIT(42);
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} else if (access_type == MMU_DATA_STORE) {
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/*
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* MCE for stores in POWER is asynchronous so hardware does
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* not set DAR, but QEMU can do better.
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*/
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env->spr[SPR_DAR] = vaddr;
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env->error_code = PPC_BIT(36) | PPC_BIT(43) | PPC_BIT(45);
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env->error_code |= PPC_BIT(42);
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} else { /* Fetch */
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/*
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* is_prefix_insn_excp() tests !PPC_BIT(42) to avoid fetching
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* the instruction, so that must always be clear for fetches.
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*/
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env->error_code = PPC_BIT(36) | PPC_BIT(44) | PPC_BIT(45);
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}
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break;
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#endif
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default:
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/*
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* TODO: Check behaviour for other CPUs, for now do nothing.
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* Could add a basic MCE even if real hardware ignores.
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*/
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return;
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}
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cs->exception_index = POWERPC_EXCP_MCHECK;
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cpu_loop_exit_restore(cs, retaddr);
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}
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void ppc_cpu_debug_excp_handler(CPUState *cs)
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{
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#if defined(TARGET_PPC64)
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CPUPPCState *env = cpu_env(cs);
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if (env->insns_flags2 & PPC2_ISA207S) {
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if (cs->watchpoint_hit) {
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if (cs->watchpoint_hit->flags & BP_CPU) {
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env->spr[SPR_DAR] = cs->watchpoint_hit->hitaddr;
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env->spr[SPR_DSISR] = PPC_BIT(41);
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cs->watchpoint_hit = NULL;
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raise_exception(env, POWERPC_EXCP_DSI);
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}
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cs->watchpoint_hit = NULL;
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} else if (cpu_breakpoint_test(cs, env->nip, BP_CPU)) {
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raise_exception_err(env, POWERPC_EXCP_TRACE,
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PPC_BIT(33) | PPC_BIT(43));
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}
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}
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#endif
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}
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bool ppc_cpu_debug_check_breakpoint(CPUState *cs)
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{
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#if defined(TARGET_PPC64)
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CPUPPCState *env = cpu_env(cs);
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if (env->insns_flags2 & PPC2_ISA207S) {
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target_ulong priv;
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priv = env->spr[SPR_CIABR] & PPC_BITMASK(62, 63);
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switch (priv) {
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case 0x1: /* problem */
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return env->msr & ((target_ulong)1 << MSR_PR);
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case 0x2: /* supervisor */
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return (!(env->msr & ((target_ulong)1 << MSR_PR)) &&
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!(env->msr & ((target_ulong)1 << MSR_HV)));
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case 0x3: /* hypervisor */
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return (!(env->msr & ((target_ulong)1 << MSR_PR)) &&
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(env->msr & ((target_ulong)1 << MSR_HV)));
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default:
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g_assert_not_reached();
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}
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}
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#endif
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return false;
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}
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bool ppc_cpu_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp)
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{
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#if defined(TARGET_PPC64)
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CPUPPCState *env = cpu_env(cs);
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if (env->insns_flags2 & PPC2_ISA207S) {
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if (wp == env->dawr0_watchpoint) {
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uint32_t dawrx = env->spr[SPR_DAWRX0];
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bool wt = extract32(dawrx, PPC_BIT_NR(59), 1);
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bool wti = extract32(dawrx, PPC_BIT_NR(60), 1);
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bool hv = extract32(dawrx, PPC_BIT_NR(61), 1);
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bool sv = extract32(dawrx, PPC_BIT_NR(62), 1);
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bool pr = extract32(dawrx, PPC_BIT_NR(62), 1);
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if ((env->msr & ((target_ulong)1 << MSR_PR)) && !pr) {
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return false;
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} else if ((env->msr & ((target_ulong)1 << MSR_HV)) && !hv) {
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return false;
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} else if (!sv) {
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return false;
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}
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if (!wti) {
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if (env->msr & ((target_ulong)1 << MSR_DR)) {
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if (!wt) {
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return false;
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}
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} else {
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if (wt) {
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return false;
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}
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}
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}
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return true;
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}
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}
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#endif
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return false;
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}
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#endif /* !CONFIG_USER_ONLY */
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