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hw/riscv: Move sifive_u_otp model to hw/misc

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This is an effort to clean up the hw/riscv directory. Ideally it
should only contain the RISC-V SoC / machine codes plus generic
codes. Let's move sifive_u_otp model to hw/misc directory.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1599129623-68957-4-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Bin Meng 2020-09-03 18:40:14 +08:00 • committed by Alistair Francis
parent 9fe640a53d
commit 0fa9e32945
7 changed files with 7 additions and 3 deletions
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2
include/hw/riscv/sifive_u.h
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@ -24,7 +24,7 @@
#include "hw/riscv/riscv_hart.h"
#include "hw/riscv/sifive_cpu.h"
#include "hw/riscv/sifive_gpio.h"
#include "hw/riscv/sifive_u_otp.h"
#include "hw/misc/sifive_u_otp.h"
#include "hw/misc/sifive_u_prci.h"
#define TYPE_RISCV_U_SOC "riscv.sifive.u.soc"