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target/arm: Conditionalize some asserts on aarch32 support

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When populating id registers from kvm, on a host that doesn't support
aarch32 mode at all, neither arm_div nor jazelle will be supported either.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Tested-by: Alex Bennée <alex.bennee@linaro.org>
Message-id: 20181102102025.3546-1-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson 2018-11-02 10:20:25 +00:00 • committed by Peter Maydell
parent 5e9fcbd7df
commit 0f8d06f16c
2 changed files with 18 additions and 2 deletions
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15
target/arm/cpu.c
View file

@ -774,6 +774,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
CPUARMState *env = &cpu->env; CPUARMState *env = &cpu->env;
int pagebits; int pagebits;
Error *local_err = NULL; Error *local_err = NULL;
bool no_aa32 = false;
/* If we needed to query the host kernel for the CPU features /* If we needed to query the host kernel for the CPU features
* then it's possible that might have failed in the initfn, but * then it's possible that might have failed in the initfn, but
@ -820,6 +821,16 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
set_feature(env, ARM_FEATURE_V7VE); set_feature(env, ARM_FEATURE_V7VE);
} }
} }
/*
* There exist AArch64 cpus without AArch32 support. When KVM
* queries ID_ISAR0_EL1 on such a host, the value is UNKNOWN.
* Similarly, we cannot check ID_AA64PFR0 without AArch64 support.
*/
if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
no_aa32 = !cpu_isar_feature(aa64_aa32, cpu);
}
if (arm_feature(env, ARM_FEATURE_V7VE)) { if (arm_feature(env, ARM_FEATURE_V7VE)) {
/* v7 Virtualization Extensions. In real hardware this implies /* v7 Virtualization Extensions. In real hardware this implies
* EL2 and also the presence of the Security Extensions. * EL2 and also the presence of the Security Extensions.
@ -829,7 +840,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
* Presence of EL2 itself is ARM_FEATURE_EL2, and of the * Presence of EL2 itself is ARM_FEATURE_EL2, and of the
* Security Extensions is ARM_FEATURE_EL3. * Security Extensions is ARM_FEATURE_EL3.
*/ */
assert(cpu_isar_feature(arm_div, cpu)); assert(no_aa32 || cpu_isar_feature(arm_div, cpu));
set_feature(env, ARM_FEATURE_LPAE); set_feature(env, ARM_FEATURE_LPAE);
set_feature(env, ARM_FEATURE_V7); set_feature(env, ARM_FEATURE_V7);
} }
@ -855,7 +866,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
if (arm_feature(env, ARM_FEATURE_V6)) { if (arm_feature(env, ARM_FEATURE_V6)) {
set_feature(env, ARM_FEATURE_V5); set_feature(env, ARM_FEATURE_V5);
if (!arm_feature(env, ARM_FEATURE_M)) { if (!arm_feature(env, ARM_FEATURE_M)) {
assert(cpu_isar_feature(jazelle, cpu)); assert(no_aa32 || cpu_isar_feature(jazelle, cpu));
set_feature(env, ARM_FEATURE_AUXCR); set_feature(env, ARM_FEATURE_AUXCR);
} }
} }

5
target/arm/cpu.h
View file

@ -3296,6 +3296,11 @@ static inline bool isar_feature_aa64_fp16(const ARMISARegisters *id)
return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, FP) == 1; return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, FP) == 1;
} }
static inline bool isar_feature_aa64_aa32(const ARMISARegisters *id)
{
return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, EL0) >= 2;
}
static inline bool isar_feature_aa64_sve(const ARMISARegisters *id) static inline bool isar_feature_aa64_sve(const ARMISARegisters *id)
{ {
return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, SVE) != 0; return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, SVE) != 0;